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| efm32 gecko family EFM32G data sheet the efm32 gecko mcus are the worlds most energy-friendly mi- crocontrollers. the EFM32G offers unmatched performance and ultra low power consumption in both active and sleep modes. EFM32G devices consume as little as 0.6 a in stop mode and 180 a/mhz in run mode. it also features autonomous peripherals, high overall chip and analog integration, and the performance of the industry standard 32-bit arm cortex-m3 processor, making it perfect for battery-powered systems and systems with high-per- formance, low-energy requirements. EFM32G applications include the following: key features ? arm cortex-m3 at 32 mhz ? ultra low power operation ? 0.6 a current in stop (em3), with brown-out detection and ram retention ? 45 a/mhz in em1 ? 180 a/mhz in run mode (em0) ? fast wake-up time of 2 s ? hardware cryptography (aes) ? up to 128 kb of flash and 16 kb of ram ? energy, gas, water and smart metering ? health and fitness applications ? smart accessories ? alarm and security systems ? industrial and home automation 32-bit bus lowest power mode with peripheral operational: em2 C deep sleep em1 - sleep em4 - shutoff em0 - active em3 - stop core / memory flash program memory ram memory arm cortex tm m3 processor debug interface dma controller memory protection unit security hardware aes energy management brown-out detector voltage regulator voltage comparator power-on reset clock management high frequency rc oscillator low frequency rc oscillator low frequency crystal oscillator watchdog oscillator auxiliary high freq. rc osc. high frequency crystal oscillator analog interfaces dac adc lcd controller analog comparator peripheral reflex system serial interfaces uart i 2 c i/o ports timers and triggers timer/counter low energy timer watchdog timer external interrupts pin reset external bus interface general purpose i/o pulse counter real time counter usart low energy uart tm silabs.com | building a more connected world. rev. 2.10
1. feature list ? arm cortex-m3 cpu platform ? high performance 32-bit processor @ up to 32 mhz ? memory protection unit ? wake-up interrupt controller ? systick system timer ? flexible energy management system ? 20 na @ 3 v shutoff mode ? 0.6 a @ 3 v stop mode, including power-on reset, brown-out detector, ram and cpu retention ? 0.9 a @ 3 v deep sleep mode, including rtc with 32.768 khz oscillator, power-on reset, brown-out detector, ram and cpu retention ? 45 a/mhz @ 3 v sleep mode ? 180 a/mhz @ 3 v run mode, with code executed from flash ? 128/64/32 kb flash ? 16/8 kb ram ? up to 90 general purpose i/o pins ? configurable push-pull, open-drain, pull-up/down, input filter, drive strength ? configurable peripheral i/o locations ? 16 asynchronous external interrupts ? output state retention and wake-up from shutoff mode ? 8 channel dma controller ? 8 channel peripheral reflex system (prs) for autonomous inter-peripheral signaling ? hardware aes with 128/256-bit keys in 54/75 cycles ? timers/counters ? 3 16-bit timer/counter ? 33 compare/capture/pwm channels ? dead-time insertion on timer0 ? 16-bit low energy timer ? 1 24-bit real-time counter ? 3 8-bit pulse counter ? watchdog timer with dedicated rc oscillator @ 50 na ? integrated lcd controller for up to 440 segments ? voltage boost, adjustable contrast and autonomous animation ? external bus interface for up to 4x64 mb of external memory mapped space ? tft controller with direct drive ? communication interfaces ? up to 3 universal synchronous/asynchronous receiver/ transmitter ? uart/spi/smartcard (iso 7816)/irda/i2s ? triple buffered full/half-duplex operation ? 1 universal asynchronous receiver/transmitter ? 2 low energy uart ? autonomous operation with dma in deep sleep mode ? i 2 c interface with smbus support ? address recognition in stop mode ? ultra low power precision analog peripherals ? 12-bit 1 msamples/s analog to digital converter ? 8 single-ended channels/4 differential channels ? on-chip temperature sensor ? 12-bit 500 ksamples/s digital to analog converter ? 2 single-ended channels/1 differential channel ? 2 analog comparator ? capacitive sensing with up to 16 inputs EFM32G data sheet feature list silabs.com | building a more connected world. rev. 2.10 | 2 ? supply voltage comparator ? ultra efficient power-on reset and brown-out detector ? 2-pin serial wire debug interface ? 1-pin serial wire viewer ? pre-programmed usb/uart bootloader ? temperature range -40 to 85 oc ? single power supply 1.98 to 3.8 v ? packages ? bga112 ? lqfp100 ? tqfp64 ? tqfp48 ? qfn64 ? qfn32 EFM32G data sheet feature list silabs.com | building a more connected world. rev. 2.10 | 3 2. ordering information the following table shows the available EFM32G devices. table 2.1. ordering information ordering code flash (kb) ram (kb) max speed (mhz) supply volt- age (v) tempera- ture (oc) package EFM32G200f16g-e-qfn32 16 8 32 1.98 - 3.8 -40 - 85 qfn32 EFM32G200f32g-e-qfn32 32 8 32 1.98 - 3.8 -40 - 85 qfn32 EFM32G200f64g-e-qfn32 64 16 32 1.98 - 3.8 -40 - 85 qfn32 EFM32G210f128g-e-qfn32 128 16 32 1.98 - 3.8 -40 - 85 qfn32 EFM32G222f32g-e-qfp48 32 8 32 1.98 - 3.8 -40 - 85 tqfp48 EFM32G222f64g-e-qfp48 64 16 32 1.98 - 3.8 -40 - 85 tqfp48 EFM32G222f128g-e-qfp48 128 16 32 1.98 - 3.8 -40 - 85 tqfp48 EFM32G230f32g-e-qfn64 32 8 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G230f64g-e-qfn64 64 16 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G230f128g-e-qfn64 128 16 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G232f32g-e-qfp64 32 8 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G232f64g-e-qfp64 64 16 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G232f128g-e-qfp64 128 16 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G280f32g-e-qfp100 32 8 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G280f64g-e-qfp100 64 16 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G280f128g-e-qfp100 128 16 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G290f32g-e-bga112 32 8 32 1.98 - 3.8 -40 - 85 bga112 EFM32G290f64g-e-bga112 64 16 32 1.98 - 3.8 -40 - 85 bga112 EFM32G290f128g-e-bga112 128 16 32 1.98 - 3.8 -40 - 85 bga112 EFM32G840f32g-e-qfn64 32 8 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G840f64g-e-qfn64 64 16 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G840f128g-e-qfn64 128 16 32 1.98 - 3.8 -40 - 85 qfn64 EFM32G842f32g-e-qfp64 32 8 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G842f64g-e-qfp64 64 16 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G842f128g-e-qfp64 128 16 32 1.98 - 3.8 -40 - 85 tqfp64 EFM32G880f32g-e-qfp100 32 8 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G880f64g-e-qfp100 64 16 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G880f128g-e-qfp100 128 16 32 1.98 - 3.8 -40 - 85 lqfp100 EFM32G890f32g-e-bga112 32 8 32 1.98 - 3.8 -40 - 85 bga112 EFM32G890f64g-e-bga112 64 16 32 1.98 - 3.8 -40 - 85 bga112 EFM32G890f128g-e-bga112 128 16 32 1.98 - 3.8 -40 - 85 bga112 EFM32G data sheet ordering information silabs.com | building a more connected world. rev. 2.10 | 4 efm32 890 128 f C bga 112 r tape and reel (optional) pin count package memory size in kb memory type (flash) feature set code gecko energy friendly microcontroller 32-bit g C e revision temperature grade C g (-40 to +85 c) g figure 2.1. ordering code decoder adding the suffix 'r' to the part number (e.g., EFM32G890f128g-e-bga112r) denotes tape and reel. visit www.silabs.com for information on global distributors and representatives. EFM32G data sheet ordering information silabs.com | building a more connected world. rev. 2.10 | 5 table of contents 1. feature list ................................ 2 2. ordering information ............................ 4 3. system overview ............................. 10 3.1 system introduction ............................ 10 3.1.1 arm cortex-m3 core ......................... 10 3.1.2 debug interface (dbg) ......................... 10 3.1.3 memory system controller (msc) ..................... 10 3.1.4 direct memory access controller (dma) ................... 11 3.1.5 reset management unit (rmu) ...................... 11 3.1.6 energy management unit (emu) ..................... 11 3.1.7 clock management unit (cmu) ...................... 11 3.1.8 watchdog (wdog) .......................... 11 3.1.9 peripheral reflex system (prs) ..................... 11 3.1.10 external bus interface (ebi) ...................... 11 3.1.11 inter-integrated circuit interface (i2c) ................... 11 3.1.12 universal synchronous/asynchronous receiver/transmitter (usart) ........ 11 3.1.13 pre-programmed usb/uart bootloader .................. 11 3.1.14 universal asynchronous receiver/transmitter (uart) ............. 12 3.1.15 low energy universal asynchronous receiver/transmitter (leuart) ........ 12 3.1.16 timer/counter (timer) ........................ 12 3.1.17 real time counter (rtc) ....................... 12 3.1.18 low energy timer (letimer) ...................... 12 3.1.19 pulse counter (pcnt) ........................ 12 3.1.20 analog comparator (acmp) ...................... 12 3.1.21 voltage comparator (vcmp) ...................... 12 3.1.22 analog to digital converter (adc) .................... 12 3.1.23 digital to analog converter (dac) .................... 12 3.1.24 advanced encryption standard accelerator (aes) ............... 13 3.1.25 general purpose input/output (gpio) ................... 13 3.1.26 liquid crystal display driver (lcd) .................... 13 3.2 configuration summary .......................... 14 3.2.1 EFM32G200 ............................ 14 3.2.2 EFM32G210 ............................ 15 3.2.3 EFM32G222 ............................ 16 3.2.4 EFM32G230 ............................ 17 3.2.5 EFM32G232 ............................ 18 3.2.6 EFM32G280 ............................ 19 3.2.7 EFM32G290 ............................ 20 3.2.8 EFM32G840 ............................ 21 3.2.9 EFM32G842 ............................ 22 3.2.10 EFM32G880 ............................ 23 3.2.11 EFM32G890 ............................ 25 3.3 memory map .............................. 27 4. electrical characteristics .......................... 29 silabs.com | building a more connected world. rev. 2.10 | 6 4.1 test conditions ............................. 29 4.1.1 typical values ........................... 29 4.1.2 minimum and maximum values ...................... 29 4.2 absolute maximum ratings ......................... 29 4.3 general operating conditions ........................ 29 4.4 current consumption ........................... 30 4.4.1 em0 current consumption ....................... 31 4.4.2 em1 current consumption ....................... 34 4.4.3 em2 current consumption ....................... 37 4.4.4 em3 current consumption ....................... 38 4.4.5 em4 current consumption ....................... 39 4.5 transition between energy modes ....................... 39 4.6 power management ............................ 40 4.7 flash ................................. 41 4.8 general purpose input output ........................ 42 4.9 oscillators ............................... 50 4.9.1 lfxo ............................... 50 4.9.2 hfxo .............................. 51 4.9.3 lfrco .............................. 52 4.9.4 hfrco .............................. 53 4.9.5 auxhfrco ............................ 57 4.9.6 ulfrco ............................. 57 4.10 analog digital converter (adc) ....................... 58 4.10.1 typical performance ......................... 67 4.11 digital analog converter (dac) ....................... 71 4.12 analog comparator (acmp) ........................ 73 4.13 voltage comparator (vcmp) ........................ 75 4.14 lcd ................................. 76 4.15 i2c ................................. 77 4.16 digital peripherals ............................ 78 5. pin definitions .............................. 79 5.1 EFM32G200 & EFM32G210 (qfn32) ...................... 79 5.1.1 pinout .............................. 79 5.1.2 alternate functionality pinout ...................... 82 5.1.3 gpio pinout overview ......................... 84 5.2 EFM32G222 (tqfp48) ........................... 85 5.2.1 pinout .............................. 85 5.2.2 alternate functionality pinout ...................... 88 5.2.3 gpio pinout overview ......................... 90 5.3 EFM32G230 (qfn64) ........................... 91 5.3.1 pinout .............................. 91 5.3.2 alternate functionality pinout ...................... 94 5.3.3 gpio pinout overview ......................... 97 silabs.com | building a more connected world. rev. 2.10 | 7 5.4 EFM32G232 (tqfp64) ........................... 98 5.4.1 pinout .............................. 98 5.4.2 alternate functionality pinout ..................... 101 5.4.3 gpio pinout overview ........................ 103 5.5 EFM32G280 (lqfp100) ......................... 104 5.5.1 pinout ............................. 104 5.5.2 alternate functionality pinout ..................... 109 5.5.3 gpio pinout overview ........................ 113 5.6 EFM32G290 (bga112) .......................... 114 5.6.1 pinout ............................. 114 5.6.2 alternate functionality pinout ..................... 119 5.6.3 gpio pinout overview ........................ 123 5.7 EFM32G840 (qfn64) .......................... 124 5.7.1 pinout ............................. 124 5.7.2 alternate functionality pinout ..................... 127 5.7.3 gpio pinout overview ........................ 131 5.8 EFM32G842 (tqfp64) .......................... 132 5.8.1 pinout ............................. 132 5.8.2 alternate functionality pinout ..................... 135 5.8.3 gpio pinout overview ........................ 139 5.9 EFM32G880 (lqfp100) ......................... 140 5.9.1 pinout ............................. 140 5.9.2 alternate functionality pinout ..................... 146 5.9.3 gpio pinout overview ........................ 152 5.10 EFM32G890 (bga112) ......................... 153 5.10.1 pinout ............................. 153 5.10.2 alternate functionality pinout ..................... 159 5.10.3 gpio pinout overview ....................... 165 6. bga112 package specifications ....................... 166 6.1 bga112 package dimensions ....................... 166 6.2 bga112 pcb layout .......................... 167 6.3 bga112 package marking ........................ 169 7. lqfp100 package specifications ....................... 170 7.1 lqfp100 package dimensions ....................... 170 7.2 lqfp100 pcb layout .......................... 172 7.3 lqfp100 package marking ........................ 174 8. tqfp64 package specifications ....................... 175 8.1 tqfp64 package dimensions ....................... 175 8.2 tqfp64 pcb layout .......................... 177 8.3 tqfp64 package marking ........................ 179 9. tqfp48 package specifications ....................... 180 9.1 tqfp48 package dimensions ....................... 180 silabs.com | building a more connected world. rev. 2.10 | 8 9.2 tqfp48 pcb layout .......................... 182 9.3 tqfp48 package marking ........................ 184 10. qfn64 package specifications ....................... 185 10.1 qfn64 package dimensions ....................... 185 10.2 qfn64 pcb layout .......................... 187 10.3 qfn64 package marking ........................ 189 11. qfn32 package specifications ....................... 190 11.1 qfn32 package dimensions ....................... 190 11.2 qfn32 pcb layout .......................... 191 11.3 qfn32 package marking ........................ 193 12. chip revision, solder information, errata ................... 194 12.1 chip revision ............................ 194 12.2 soldering information .......................... 194 12.3 errata ............................... 194 13. revision history ............................. 195 13.1 revision 2.10 ............................ 195 13.2 revision 2.00 ............................ 196 13.3 revision 1.90 ............................ 197 13.4 revision 1.80 ............................ 197 13.5 revision 1.71 ............................ 198 13.6 revision 1.70 ............................ 198 13.7 revision 1.60 ............................ 198 13.8 revision 1.50 ............................ 198 13.9 revision 1.40 ............................ 199 13.10 revision 1.30 ............................ 199 13.11 revision 1.20 ............................ 200 13.12 revision 1.11 ............................ 200 13.13 revision 1.10 ............................ 201 13.14 revision 1.00 ............................ 201 13.15 revision 0.90 ............................ 202 13.16 revision 0.85 ............................ 202 13.17 revision 0.84 ............................ 202 13.18 revision 0.83 ............................ 202 13.19 revision 0.82 ............................ 203 13.20 revision 0.81 ............................ 203 13.21 revision 0.80 ............................ 204 silabs.com | building a more connected world. rev. 2.10 | 9 3. system overview 3.1 system introduction the efm32 mcus are the worlds most energy friendly microcontrollers. with a unique combination of the powerful 32-bit arm cortex- m3 , innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy consumption. this section gives a short introduction to each of the modules in general terms and also shows a summary of the configu- ration for the EFM32G devices. for a complete feature set and in-depth information on the modules, the reader is referred to the EFM32G reference manual. the diagram shows a superset of features available on the family, which vary by opn. for more information about specific device fea- tures, consult ordering information. 32-bit bus lowest power mode with peripheral operational: em2 C deep sleep em1 - sleep em4 - shutoff em0 - active em3 - stop core / memory flash program memory ram memory arm cortex tm m3 processor debug interface dma controller memory protection unit security hardware aes energy management brown-out detector voltage regulator voltage comparator power-on reset clock management high frequency rc oscillator low frequency rc oscillator low frequency crystal oscillator watchdog oscillator auxiliary high freq. rc osc. high frequency crystal oscillator analog interfaces dac adc lcd controller analog comparator peripheral reflex system serial interfaces uart i 2 c i/o ports timers and triggers timer/counter low energy timer watchdog timer external interrupts pin reset external bus interface general purpose i/o pulse counter real time counter usart low energy uart tm figure 3.1. block diagram 3.1.1 arm cortex-m3 core the arm cortex-m3 includes a 32-bit risc processor which can achieve as much as 1.25 dhrystone mips/mhz. a memory protection unit with support for up to 8 memory segments is included, as well as a wake-up interrupt controller handling interrupts triggered while the cpu is asleep. the efm32 implementation of the cortex-m3 is described in detail in EFM32G reference manual. 3.1.2 debug interface (dbg) this device includes hardware debug support through a 2-pin serial-wire debug interface . in addition there is also a 1-wire serial wire viewer pin which can be used to output profiling information, data trace and software-generated messages. 3.1.3 memory system controller (msc) the memory system controller (msc) is the program memory unit of the EFM32G microcontroller. the flash memory is readable and writable from both the cortex- m3 and dma. the flash memory is divided into two blocks; the main block and the information block. program code is normally written to the main block. additionally, the information block is available for special user data and flash lock bits. there is also a read-only page in the information block containing system and device calibration data. read and write operations are supported in the energy modes em0 and em1. EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 10 3.1.4 direct memory access controller (dma) the direct memory access (dma) controller performs memory operations independently of the cpu. this has the benefit of reducing the energy consumption and the workload of the cpu, and enables the system to stay in low energy modes when moving for instance data from the usart to ram or from the external bus interface to a pwm-generating timer. the dma controller uses the pl230 dma controller licensed from arm. 3.1.5 reset management unit (rmu) the rmu is responsible for handling the reset functionality of the EFM32G. 3.1.6 energy management unit (emu) the energy management unit (emu) manage all the low energy modes (em) in EFM32G microcontrollers. each energy mode man- ages if the cpu and the various peripherals are available. the emu can also be used to turn off the power to unused sram blocks. 3.1.7 clock management unit (cmu) the clock management unit (cmu) is responsible for controlling the oscillators and clocks on-board the EFM32G . the cmu provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. the high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive. 3.1.8 watchdog (wdog) the purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. the failure may e.g. be caused by an external event, such as an esd pulse, or by a software failure. 3.1.9 peripheral reflex system (prs) the peripheral reflex system (prs) system is a network which lets the different peripheral module communicate directly with each other without involving the cpu. peripheral modules which send out reflex signals are called producers. the prs routes these reflex signals to consumer peripherals which apply actions depending on the data received. the format for the reflex signals is not given, but edge triggers and other functionality can be applied by the prs. 3.1.10 external bus interface (ebi) the external bus interface provides access to external parallel interface devices such as sram, flash, adcs and lcds. the inter- face is memory mapped into the address bus of the cortex-m3. this enables seamless access from software without manually manipu- lating the io settings each time a read or write is performed. the data and address lines are multiplexed in order to reduce the number of pins required to interface the external devices. the timing is adjustable to meet specifications of the external devices. the interface is limited to asynchronous devices. 3.1.11 inter-integrated circuit interface (i2c) the i 2 c module provides an interface between the mcu and a serial i 2 c-bus. it is capable of acting as both a master and a slave, and supports multi-master buses. both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 mbit/s. slave arbitration and timeouts are also provided to allow implementation of an smbus compliant system. the interface provided to software by the i 2 c module, allows both fine-grained control of the transmission process and close to automatic transfers. automatic recognition of slave addresses is provided in all energy modes. 3.1.12 universal synchronous/asynchronous receiver/transmitter (usart) the universal synchronous asynchronous serial receiver and transmitter (usart) is a very flexible serial i/o module. it supports full duplex asynchronous uart communication as well as rs-485, spi, microwire and 3-wire. it can also interface with iso7816 smart- cards, and irda devices. 3.1.13 pre-programmed usb/uart bootloader the bootloader presented in application note an0003 is pre-programmed in the device at factory. autobaud and destructive write are supported. the autobaud feature, interface and commands are described further in the application note. EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 11 3.1.14 universal asynchronous receiver/transmitter (uart) the universal asynchronous serial receiver and transmitter (uart) is a very flexible serial i/o module. it supports full- and half-du- plex asynchronous uart communication. 3.1.15 low energy universal asynchronous receiver/transmitter (leuart) the unique leuart tm , the low energy uart, is a uart that allows two-way uart communication on a strict power budget. only a 32.768 khz clock is needed to allow uart communication up to 9600 baud/ s. the leuart includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption. 3.1.16 timer/counter (timer) the 16-bit general purpose timer has 3 compare/capture channels for input capture and compare/pulse-width modulation (pwm) out- put. timer0 also includes a dead-time insertion module suitable for motor control applications. 3.1.17 real time counter (rtc) the real time counter (rtc) contains a 24-bit counter and is clocked either by a 32.768 khz crystal oscillator, or a 32.768 khz rc oscillator. in addition to energy modes em0 and em1, the rtc is also available in em2. this makes it ideal for keeping track of time since the rtc is enabled in em2 where most of the device is powered down. 3.1.18 low energy timer (letimer) the unique letimer tm , the low energy timer, is a 16-bit timer that is available in energy mode em2 in addition to em1 and em0. because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. the letimer can be used to output a variety of waveforms with minimal software intervention. it is also connected to the real time counter (rtc), and can be configured to start counting on compare matches from the rtc. 3.1.19 pulse counter (pcnt) the pulse counter (pcnt) can be used for counting pulses on a single input or to decode quadrature encoded inputs. it runs off either the internal lfaclk or the pcntn_s0in pin as external clock source. the module may operate in energy mode em0 - em3. 3.1.20 analog comparator (acmp) the analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high- er. inputs can either be one of the selectable internal references or from external pins. response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.21 voltage comparator (vcmp) the voltage supply comparator is used to monitor the supply voltage from software. an interrupt can be generated when the supply falls below or rises above a programmable threshold. response time and thereby also the current consumption can be configured by altering the current supply to the comparator. 3.1.22 analog to digital converter (adc) the adc is a successive approximation register (sar) architecture, with a resolution of up to 12 bits at up to one million samples per second. the integrated input mux can select inputs from 8 external pins and 6 internal signals. 3.1.23 digital to analog converter (dac) the digital to analog converter (dac) can convert a digital value to an analog output voltage. the dac is fully differential rail-to-rail, with 12-bit resolution. it has two single-ended output buffers which can be combined into one differential output. the dac may be used for a number of different applications such as sensor interfaces or sound output. EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 12 3.1.24 advanced encryption standard accelerator (aes) the aes accelerator performs aes encryption and decryption with 128-bit or 256-bit keys. encrypting or decrypting one 128-bit data block takes 52 hfcoreclk cycles with 128-bit keys and 75 hfcoreclk cycles with 256-bit keys. the aes module is an ahb slave which enables efficient access to the data and key registers. all write accesses to the aes module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 3.1.25 general purpose input/output (gpio) general purpose input/output (gpio) pins are organized into ports with up to 16 pins each. these pins can individually be configured as either an output or input. more advanced configurations like open-drain, filtering and drive strength can also be configured individual- ly for the pins. the gpio pins can also be overridden by peripheral pin connections, like timer pwm outputs or usart communica- tion, which can be routed to several locations on the device. the gpio supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. also, the input value of a pin can be routed through the peripheral reflex system to other peripherals. 3.1.26 liquid crystal display driver (lcd) the lcd driver is capable of driving a segmented lcd display with up to 4x40 segments. a voltage boost function enables it to provide the lcd display with higher voltage than the supply voltage for the device. in addition, an animation feature can run custom animations on the lcd display without any cpu intervention. the lcd driver can also remain active even in energy mode 2 and provides a frame counter interrupt that can wake-up the device on a regular basis for updating data. EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 13 3.2 configuration summary 3.2.1 EFM32G200 the features of the EFM32G200 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.1. EFM32G200 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs leuart0 full configuration leu0_tx, leu0_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] acmp0 full configuration acmp0_ch[1:0], acmp0_o acmp1 full configuration acmp1_ch[7:5], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:4] dac0 full configuration dac0_out[0] gpio 24 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 14 3.2.2 EFM32G210 the features of the EFM32G210 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.2. EFM32G210 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs leuart0 full configuration leu0_tx, leu0_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] acmp0 full configuration acmp0_ch[1:0], acmp0_o acmp1 full configuration acmp1_ch[7:5], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:4] dac0 full configuration dac0_out[0] aes full configuration na gpio 24 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 15 3.2.3 EFM32G222 the features of the EFM32G222 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.3. EFM32G222 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs leuart0 full configuration leu0_tx, leu0_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] acmp0 full configuration acmp0_ch[4:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:4] dac0 full configuration dac0_out[1] aes full configuration na gpio 37 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 16 3.2.4 EFM32G230 the features of the EFM32G230 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.4. EFM32G230 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 56 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 17 3.2.5 EFM32G232 the features of the EFM32G232 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.5. EFM32G232 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[15:8], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[0] aes full configuration na gpio 53 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 18 3.2.6 EFM32G280 the features of the EFM32G280 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.6. EFM32G280 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na ebi full configuration ebi_ardy, ebi_ale, ebi_wen, ebi_ren, ebi_cs[3:0], ebi_ad[15:0] i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs uart0 full configuration u0_tx, u0_rx leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 86 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 19 3.2.7 EFM32G290 the features of the EFM32G290 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.7. EFM32G290 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na ebi full configuration ebi_ardy, ebi_ale, ebi_wen, ebi_ren, ebi_cs[3:0], ebi_ad[15:0] i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs uart0 full configuration u0_tx, u0_rx leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 90 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 20 3.2.8 EFM32G840 the features of the EFM32G840 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.8. EFM32G840 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:4], acmp0_o acmp1 full configuration acmp1_ch[7:4], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 56 pins available pins are shown in table 4.3 (p. 57) lcd full configuration lcd_seg[23:0], lcd_com[3:0], lcd_bcap_p, lcd_bcap_n, lcd_bext EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 21 3.2.9 EFM32G842 the features of the EFM32G842 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.9. EFM32G842 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[3:0], acmp0_o acmp1 full configuration acmp1_ch[7:4], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[0] aes full configuration na gpio 53 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 22 3.2.10 EFM32G880 the features of the EFM32G880 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.10. EFM32G880 configuration summary module module module cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na ebi full configuration ebi_ardy, ebi_ale, ebi_wen, ebi_ren, ebi_cs[3:0], ebi_ad[15:0] i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs uart0 full configuration u0_tx, u0_rx leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 86 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 23 module module module lcd full configuration lcd_seg[39:0], lcd_com[3:0], lcd_bcap_p, lcd_bcap_n, lcd_bext EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 24 3.2.11 EFM32G890 the features of the EFM32G890 is a subset of the feature set described in the EFM32G reference manual. the following table de- scribes device specific implementation of the features. table 3.11. EFM32G890 configuration summary module configuration pin connections cortex-m3 full configuration na dbg full configuration dbg_swclk, dbg_swdio, dbg_swo msc full configuration na dma full configuration na rmu full configuration na emu full configuration na cmu full configuration cmu_out0, cmu_out1 wdog full configuration na prs full configuration na ebi full configuration ebi_ardy, ebi_ale, ebi_wen, ebi_ren, ebi_cs[3:0], ebi_ad[15:0] i2c0 full configuration i2c0_sda, i2c0_scl usart0 full configuration with irda us0_tx, us0_rx. us0_clk, us0_cs usart1 full configuration us1_tx, us1_rx, us1_clk, us1_cs usart2 full configuration us2_tx, us2_rx, us2_clk, us2_cs uart0 full configuration u0_tx, u0_rx leuart0 full configuration leu0_tx, leu0_rx leuart1 full configuration leu1_tx, leu1_rx timer0 full configuration with dti tim0_cc[2:0], tim0_cdti[2:0] timer1 full configuration tim1_cc[2:0] timer2 full configuration tim2_cc[2:0] rtc full configuration na letimer0 full configuration let0_o[1:0] pcnt0 full configuration, 8-bit count register pcnt0_s[1:0] pcnt1 full configuration, 8-bit count register pcnt1_s[1:0] pcnt2 full configuration, 8-bit count register pcnt2_s[1:0] acmp0 full configuration acmp0_ch[7:0], acmp0_o acmp1 full configuration acmp1_ch[7:0], acmp1_o vcmp full configuration na adc0 full configuration adc0_ch[7:0] dac0 full configuration dac0_out[1:0] aes full configuration na gpio 90 pins available pins are shown in table 4.3 (p. 57) EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 25 module configuration pin connections lcd full configuration lcd_seg[39:0], lcd_com[7:0], lcd_bcap_p, lcd_bcap_n, lcd_bext EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 26 3.3 memory map the EFM32G memory map is shown in the figure below. ram and flash sizes are for the largest memory configuration. figure 3.2. system address space with core and code space listing EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 27 figure 3.3. system address space with peripheral listing EFM32G data sheet system overview silabs.com | building a more connected world. rev. 2.10 | 28 4. electrical characteristics 4.1 test conditions 4.1.1 typical values the typical data are based on t amb =25c and v dd =3.0 v, as defined in table 4.2 general operating conditions on page 29 , unless otherwise specified. 4.1.2 minimum and maximum values the minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in table 4.2 general operating conditions on page 29 , unless otherwise specified. 4.2 absolute maximum ratings the absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. stress beyond the limits specified in the following table may affect the device reliability or cause permanent damage to the device. functional operat- ing conditions are given in table 4.2 general operating conditions on page 29 . table 4.1. absolute maximum ratings parameter symbol test condition min typ max unit storage temperature range t stg -40 150 c maximum soldering temperature t s latest ipc/jedec j- std-020 standard 260 c external main supply voltage v ddmax 0 3.8 v voltage on any i/o pin v iopin -0.3 v dd +0.3 v current per i/o pin (sink) i iomax_sink 100 ma current per i/o pin (source) i iomax_source -100 ma 4.3 general operating conditions table 4.2. general operating conditions parameter symbol min typ max unit ambient temperature range t amb -40 85 c operating supply voltage v ddop 1.98 3.8 v internal apb clock frequency f apb 32 mhz internal ahb clock frequency f ahb 32 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 29 4.4 current consumption table 4.3. current consumption parameter symbol test condition min typ max unit em0 current. no prescaling. running prime number cal- culation code from flash. (production test condition = 14 mhz) i em0 32 mhz hfxo, all peripheral clocks disabled, v dd = 3.0 v 180 a/mhz 28 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 181 206 a/mhz 21 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 183 207 a/mhz 14 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 185 211 a/mhz 11 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 186 215 a/mhz 6.6 mhz hfrco, all peripheral clocks disa- bled, v dd = 3.0 v 191 218 a/mhz 1.2 mhz hfrco, all peripheral clocks disa- bled, v dd = 3.0 v 220 a/mhz em1 current (production test condition = 14 mhz) i em1 32 mhz hfxo, all peripheral clocks disabled, v dd = 3.0 v 45 a/mhz 28 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 47 62 a/mhz 21 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 48 64 a/mhz 14 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 50 69 a/mhz 11 mhz hfrco, all peripheral clocks disabled, v dd = 3.0 v 51 72 a/mhz 6.6 mhz hfrco, all peripheral clocks disa- bled, v dd = 3.0 v 56 83 a/mhz 1.2 mhz hfrco. all peripheral clocks disa- bled, v dd = 3.0 v 103 a/mhz em2 current i em2 em2 current with rtc prescaled to 1 hz, 32.768 khz lfrco, v dd = 3.0 v, t amb =25 oc 0.9 1.5 a em2 current with rtc prescaled to 1 hz, 32.768 khz lfrco, v dd = 3.0 v, t amb =85 oc 3.0 6.0 a em3 current i em3 v dd = 3.0 v, t amb =25 oc 0.59 1.0 a v dd = 3.0 v, t amb =85 oc 2.75 5.8 a em4 current i em4 v dd = 3.0 v, t amb =25 oc 0.02 0.045 a v dd = 3.0 v, t amb =85 oc 0.25 0.7 a EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 30 4.4.1 em0 current consumption 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 idd [ma] vdd=2.0v vdd=2.2v vdd=2.4v vdd=2.6v vdd=2.8v vdd=3.0v vdd=3.2v vdd=3.4v vdd=3.6v vdd=3.8v figure 4.1. em0 current consumption while executing prime number calculation code from flash with hfrco running at 28 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 31 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 3.5 3.6 3.7 3.8 3.9 4.0 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 3.5 3.6 3.7 3.8 3.9 4.0 idd [ma] vdd=2.0v vdd=2.2v vdd=2.4v vdd=2.6v vdd=2.8v vdd=3.0v vdd=3.2v vdd=3.4v vdd=3.6v vdd=3.8v figure 4.2. em0 current consumption while executing prime number calculation code from flash with hfrco running at 21 mhz 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 idd [ma] vdd=2.0v vdd=2.2v vdd=2.4v vdd=2.6v vdd=2.8v vdd=3.0v vdd=3.2v vdd=3.4v vdd=3.6v vdd=3.8v figure 4.3. em0 current consumption while executing prime number calculation code from flash with hfrco running at 14 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 32 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 idd [ma] vdd=2.0v vdd=2.2v vdd=2.4v vdd=2.6v vdd=2.8v vdd=3.0v vdd=3.2v vdd=3.4v vdd=3.6v vdd=3.8v figure 4.4. em0 current consumption while executing prime number calculation code from flash with hfrco running at 11 mhz C40 C15 5 25 45 65 85 temperature [c] 1.20 1.25 1.30 1.35 1.40 1.45 idd [ma] vdd=2.0v vdd=2.2v vdd=2.4v vdd=2.6v vdd=2.8v vdd=3.0v vdd=3.2v vdd=3.4v vdd=3.6v vdd=3.8v 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 1.20 1.25 1.30 1.35 1.40 1.45 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c figure 4.5. em0 current consumption while executing prime number calculation code from flash with hfrco running at 7 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 33 4.4.2 em1 current consumption 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 1.15 1.20 1.25 1.30 1.35 1.40 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 1.15 1.20 1.25 1.30 1.35 1.40 idd [ma] vdd=2.0v vdd=2.4v vdd=2.8v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.6. em1 current consumption with all peripheral clocks disabled and hfrco running at 28 mhz 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 idd [ma] vdd=2.0v vdd=2.4v vdd=2.8v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.7. em1 current consumption with all peripheral clocks disabled and hfrco running at 21 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 34 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.64 0.66 0.68 0.70 0.72 0.74 0.76 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.64 0.66 0.68 0.70 0.72 0.74 0.76 idd [ma] vdd=2.0v vdd=2.4v vdd=2.8v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.8. em1 current consumption with all peripheral clocks disabled and hfrco running at 14 mhz 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.52 0.54 0.56 0.58 0.60 0.62 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.52 0.54 0.56 0.58 0.60 0.62 idd [ma] vdd=2.0v vdd=2.4v vdd=2.8v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.9. em1 current consumption with all peripheral clocks disabled and hfrco running at 11 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 35 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 idd [ma] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 idd [ma] vdd=2.0v vdd=2.4v vdd=2.8v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.10. em1 current consumption with all peripheral clocks disabled and hfrco running at 7 mhz EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 36 4.4.3 em2 current consumption 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 idd [ua] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 idd [ua] vdd=1.8v vdd=2.2v vdd=2.6v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.11. em2 current consumption, rtc prescaled to 1 khz, 32.768 khz lfrco EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 37 4.4.4 em3 current consumption 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 idd [ua] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 idd [ua] vdd=1.8v vdd=2.2v vdd=2.6v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.12. em3 current consumption EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 38 4.4.5 em4 current consumption 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd [v] 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 idd [ua] -40.0c -15.0c 5.0c 25.0c 45.0c 65.0c 85.0c C40 C15 5 25 45 65 85 temperature [c] 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 idd [ua] vdd=1.8v vdd=2.2v vdd=2.6v vdd=3.0v vdd=3.4v vdd=3.8v figure 4.13. em4 current consumption 4.5 transition between energy modes the transition times are measured from the trigger to the first clock edge in the cpu. table 4.4. energy modes transitions parameter symbol min typ max unit transition time from em1 to em0 t em10 0 hfcoreclk cycles transition time from em2 to em0 t em20 2 s transition time from em3 to em0 t em30 2 s transition time from em4 to em0 t em40 163 s EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 39 4.6 power management the EFM32G requires the avdd_x, vdd_dreg and iovdd_x pins to be connected together (with optional filter) at the pcb level. for practical schematic recommendations, please see the application note, "an0002 efm32 hardware design considerations". table 4.5. power management parameter symbol test condition min typ max unit bod threshold on falling external sup- ply voltage v bodextthr- em0 1.74 1.96 v em1 1.74 1.96 v em2 1.74 1.96 v bod threshold on rising external sup- ply voltage v bodextthr+ em0 1.85 v power-on reset (por) threshold on rising external supply voltage v porthr+ 1.98 v delay from reset is released until pro- gram execution starts t resetdly applies to power-on re- set, brown-out reset and pin reset. 163 s negative pulse length to ensure com- plete reset of device t reset 50 ns voltage regulator decoupling capaci- tor. c decouple x5r capacitor recom- mended. apply between decouple pin and ground 1 f EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 40 4.7 flash table 4.6. flash parameter symbol test condition min typ max unit flash erase cycles before failure ec flash 20000 cycles flash data retention ret flash t amb <150 oc 10000 h t amb <85 oc 10 years t amb <70 oc 20 years word (32-bit) programming time t w_prog 20 s page erase time 2 t p_erase 20.7 22.0 24.8 ms device erase time 3 t d_erase 41.8 45.0 49.2 ms erase current i erase 7 1 ma write current i write 7 1 ma supply voltage during flash erase and write v flash 1.98 3.8 v note: 1. measured at 25 c. 2. from setting erasepage bit in msc_writecmd to 1 to reading 1 in erase bit in msc_if. internal setup and hold times for flash control signals are included. 3. from setting deviceerase bit in aap_cmd to 1 to reading 0 in erasebusy bit in aap_status. internal setup and hold times for flash control signals are included. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 41 4.8 general purpose input output table 4.7. gpio parameter symbol test condition min typ max unit input low voltage v ioil 0.30v dd 1 v input high voltage v ioih 0.70v dd 1 v output high voltage (production test condition = 3.0 v, drive- mode = standard) v iooh sourcing 0.1 ma, v dd =1.98 v, gpio_px_ctrl drivemode = lowest 0.80v dd v sourcing 0.1 ma, v dd =3.0 v, gpio_px_ctrl drivemode = lowest 0.90v dd v sourcing 1 ma, v dd =1.98 v, gpio_px_ctrl drivemode = low 0.85v dd v sourcing 1 ma, v dd =3.0 v, gpio_px_ctrl drivemode = low 0.90v dd v sourcing 6 ma, v dd =1.98 v, gpio_px_ctrl drivemode = standard 0.75v dd v sourcing 6 ma, v dd =3.0 v, gpio_px_ctrl drivemode = standard 0.85v dd v sourcing 20 ma, v dd =1.98 v, gpio_px_ctrl drivemode = high 0.60v dd v sourcing 20 ma, v dd =3.0 v, gpio_px_ctrl drivemode = high 0.80v dd v EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 42 parameter symbol test condition min typ max unit output low voltage (production test condition = 3.0 v, drive- mode = standard) v iool sinking 0.1 ma, v dd =1.98 v, gpio_px_ctrl drivemode = lowest 0.20v dd v sinking 0.1 ma, v dd =3.0 v, gpio_px_ctrl drivemode = lowest 0.10v dd v sinking 1 ma, v dd =1.98 v, gpio_px_ctrl drivemode = low 0.10v dd v sinking 1 ma, v dd =3.0 v, gpio_px_ctrl drivemode = low 0.05v dd v sinking 6 ma, v dd =1.98 v, gpio_px_ctrl drivemode = standard 0.30v dd v sinking 6 ma, v dd =3.0 v, gpio_px_ctrl drivemode = standard 0.20v dd v sinking 20 ma, v dd =1.98 v, gpio_px_ctrl drivemode = high 0.35v dd v sinking 20 ma, v dd =3.0 v, gpio_px_ctrl drivemode = high 0.25v dd v input leakage current i ioleak high impedance io connected to ground or v dd 0.1 40 na i/o pin pull-up resistor r pu 40 k i/o pin pull-down resistor r pd 40 k internal esd series resistor r ioesd 200 pulse width of pulses to be re- moved by the glitch suppres- sion filter t ioglitch 10 50 ns output fall time t ioof gpio_px_ctrl drivemode = lowest and load capaci- tance c l =12.5-25pf. 20+0.1c l 250 ns gpio_px_ctrl drivemode = low and load capacitance c l =350-600pf 20+0.1c l 250 ns i/o pin hysteresis (v iothr+ - v iothr- ) v iohyst v dd = 1.98 - 3.8 v 0.1v dd v note: 1. if the gpio input voltage is between 0.3v dd and 0.7v dd , the current consumption will increase. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 43 0.0 0.5 1.0 1.5 2.0 low-level output voltage [v] 0.00 0.05 0.10 0.15 0.20 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest 0.0 0.5 1.0 1.5 2.0 low-level output voltage [v] 0 5 10 15 20 25 30 35 40 45 low-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 low-level output voltage [v] 0 5 10 15 20 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = low 0.0 0.5 1.0 1.5 2.0 low-level output voltage [v] 0 1 2 3 4 5 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = standard gpio_px_ctrl drivemode = high figure 4.14. typical low-level output current, 2v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 44 0.0 0.5 1.0 1.5 2.0 high-level output voltage [v] C0.20 C0.15 C0.10 C0.05 0.00 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest 0.0 0.5 1.0 1.5 2.0 high-level output voltage [v] C2.5 C2.0 C1.5 C1.0 C0.5 0.0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = low 0.0 0.5 1.0 1.5 2.0 high-level output voltage [v] C20 C15 C10 C5 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = standard 0.0 0.5 1.0 1.5 2.0 high-level output voltage [v] C50 C40 C30 C20 C10 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = high figure 4.15. typical high-level output current, 2v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 45 0.0 0.5 1.0 1.5 2.0 2.5 3.0 low-level output voltage [v] 0 2 4 6 8 10 low-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 low-level output voltage [v] 0.0 0.1 0.2 0.3 0.4 0.5 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest gpio_px_ctrl drivemode = low 0.0 0.5 1.0 1.5 2.0 2.5 3.0 low-level output voltage [v] 0 10 20 30 40 50 low-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 low-level output voltage [v] 0 5 10 15 20 25 30 35 40 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = standard gpio_px_ctrl drivemode = high figure 4.16. typical low-level output current, 3v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 46 0.0 0.5 1.0 1.5 2.0 2.5 3.0 high-level output voltage [v] C6 C5 C4 C3 C2 C1 0 high-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 high-level output voltage [v] C0.5 C0.4 C0.3 C0.2 C0.1 0.0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest gpio_px_ctrl drivemode = low 0.0 0.5 1.0 1.5 2.0 2.5 3.0 high-level output voltage [v] C50 C40 C30 C20 C10 0 high-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 high-level output voltage [v] C50 C40 C30 C20 C10 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = standard gpio_px_ctrl drivemode = high figure 4.17. typical high-level output current, 3v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 47 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 low-level output voltage [v] 0 10 20 30 40 50 low-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 low-level output voltage [v] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 low-level output voltage [v] 0 10 20 30 40 50 low-level output current [ma] -40c 25c 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 low-level output voltage [v] 0 2 4 6 8 10 12 14 low-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = low gpio_px_ctrl drivemode = standard gpio_px_ctrl drivemode = high figure 4.18. typical low-level output current, 3.8v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 48 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 high-level output voltage [v] C0.8 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0.0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = lowest 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 high-level output voltage [v] C9 C8 C7 C6 C5 C4 C3 C2 C1 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = low 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 high-level output voltage [v] C50 C40 C30 C20 C10 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = standard 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 high-level output voltage [v] C50 C40 C30 C20 C10 0 high-level output current [ma] -40c 25c 85c gpio_px_ctrl drivemode = high figure 4.19. typical high-level output current, 3.8v supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 49 4.9 oscillators 4.9.1 lfxo table 4.8. lfxo parameter symbol test condition min typ max unit supported nominal crystal fre- quency f lfxo 32.768 khz supported crystal equivalent ser- ies resistance (esr) esr lfxo 30 120 kohm supported crystal external load range c lfxol x 1 25 pf current consumption for core and buffer after startup i lfxo esr=30 k, c l =10 pf, lfxo- boost in cmu_ctrl is 1 190 na start-up time t lfxo esr=30 k, c l =10 pf, 40% - 60% duty cycle has been reached, lfxoboost in cmu_ctrl is 1 400 ms note: 1. see minimum load capacitance (c lfxol ) requirement for safe crystal startup in configurator in simplicity studio. for safe startup of a given crystal, the configurator tool in simplicity studio contains a tool to help users configure both load capaci- tance and software settings for using the lfxo. for details regarding the crystal configuration, the reader is referred to application note "an0016 efm32 oscillator design consideration". EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 50 4.9.2 hfxo table 4.9. hfxo parameter symbol test condition min typ max unit supported nominal crystal fre- quency f hfxo 4 32 mhz supported crystal equivalent ser- ies resistance (esr) esr hfxo crystal frequency 32 mhz 30 60 crystal frequency 4 mhz 400 1500 the transconductance of the hfxo input transistor at crystal startup g mhfxo hfxoboost in cmu_ctrl equals 0b11 20 ms supported crystal external load range c hfxol 5 25 pf current consumption for hfxo after startup i hfxo 4 mhz: esr=400 , c l =20 pf, hfxoboost in cmu_ctrl equals 0b11 85 a 32 mhz: esr=30 , c l =10 pf, hfxoboost in cmu_ctrl equals 0b11 165 a startup time t hfxo 32 mhz: esr=30 , c l =10 pf, hfxoboost in cmu_ctrl equals 0b11 400 s pulse width removed by glitch de- tector 1 4 ns EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 51 4.9.3 lfrco table 4.10. lfrco parameter symbol test condition min typ max unit oscillation frequency, v dd = 3.0 v, t amb =25c f lfrco 31.29 32.768 34.24 khz startup time not including soft- ware calibration t lfrco 150 s current consumption i lfrco 190 na temperature coefficient tc lfrco 0.02 %/c supply voltage coefficient vc lfrco 15 %/v frequency step for lsb change in tuning value tunestep lfrco 1.5 % figure 4.20. calibrated lfrco frequency vs temperature and supply voltage EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 52 4.9.4 hfrco table 4.11. hfrco parameter symbol test condition min typ max unit oscillation frequency, v dd = 3.0 v, t amb =25 oc f hfrco 28 mhz frequency band 27.16 28 28.84 mhz 21 mhz frequency band 20.37 21 21.63 mhz 14 mhz frequency band 13.58 14 14.42 mhz 11 mhz frequency band 10.67 11 11.33 mhz 7 mhz frequency band 6.402 6.6 1 6.798 mhz 1 mhz frequency band 1.164 1.2 2 1.236 mhz settling time t hfrco_settling after start-up, f hfrco = 14 mhz 0.6 cycles after band switch 25 cycles current consumption (produc- tion test condition = 14 mhz) i hfrco f hfrco = 28 mhz 158 190 a f hfrco = 21 mhz 125 155 a f hfrco = 14 mhz 99 120 a f hfrco = 11 mhz 88 110 a f hfrco = 6.6 mhz 72 90 a f hfrco = 1.2 mhz 24 32 a duty cycle dc hfrco f hfrco = 14 mhz 48.5 50 51 % frequency step for lsb change in tuning value tunestep hfrco 0.3 3 % note: 1. for devices with prod. rev. < 19, typ = 7 mhz and min/max values not applicable. 2. for devices with prod. rev. < 19, typ = 1 mhz and min/max values not applicable. 3. the tuning field in the cmu_hfrcoctrl register may be used to adjust the hfrco frequency. there is enough adjustment range to ensure that the frequency bands above 7 mhz will always have some overlap across supply voltage and temperature. by using a stable frequency reference such as the lfxo or hfxo, a firmware calibration routine can vary the tuning bits and the frequency band to maintain the hfrco frequency at any arbitrary value between 7 mhz and 28 mhz across operating condi- tions. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 53 figure 4.21. calibrated hfrco 1 mhz band frequency vs supply voltage and temperature figure 4.22. calibrated hfrco 7 mhz band frequency vs supply voltage and temperature EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 54 figure 4.23. calibrated hfrco 11 mhz band frequency vs supply voltage and temperature figure 4.24. calibrated hfrco 14 mhz band frequency vs supply voltage and temperature EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 55 figure 4.25. calibrated hfrco 21 mhz band frequency vs supply voltage and temperature figure 4.26. calibrated hfrco 28 mhz band frequency vs supply voltage and temperature EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 56 4.9.5 auxhfrco table 4.12. auxhfrco parameter symbol test condition min typ max unit oscillation frequency, v dd = 3.0 v, t amb =25 oc f auxhfrco 14 mhz frequency band 13.580 14.0 14.420 mhz settling time after start-up t auxhfrco_settling f auxhfrco = 14 mhz 0.6 cycles duty cycle dc auxhfrco f auxhfrco = 14 mhz 48.5 50 51 % frequency step for lsb change in tuning value tunestep auxhfrco 0.3 1 % note: 1. the tuning field in the cmu_auxhfrcoctrl register may be used to adjust the auxhfrco frequency. by using a stable frequency reference such as the lfxo or hfxo, a firmware calibration routine can vary the tuning bits and the frequency band to maintain the auxhfrco frequency at any arbitrary value in the 14 mhz range across operating conditions. 4.9.6 ulfrco table 4.13. ulfrco parameter symbol test condition min typ max unit oscillation frequency f ulfrco 25 c, 3 v 0.7 1.75 khz temperature coefficient tc ulfrco 0.05 %/c supply voltage coefficient vc ulfrco -18.2 %/v EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 57 4.10 analog digital converter (adc) table 4.14. adc parameter symbol test condition min typ max unit input voltage range v adcin single-ended 0 v ref v differential -v ref /2 v ref /2 v input range of external refer- ence voltage, single-ended and differential v adcrefin 1.25 v dd v input range of external negative reference voltage on channel 7 v adcrefin_ch7 see v adcrefin 0 v dd - 1.1 v input range of external positive reference voltage on channel 6 v adcrefin_ch6 see v adcrefin 0.625 v dd v common mode input range v adccmin 0 v dd v input current i adcin 2 pf sampling capacitors <100 na analog input common mode re- jection ratio cmrr adc 65 db average active current i adc 1 msamples/s, 12 bit, external reference, adc_clk = 13 mhz, biasprog = 0xf4b 735 1 a 1 msamples/s, 12 bit, internal 1.25v reference, adc_clk = 13 mhz, biasprog = 0xf4b 760 1 a 500 ksamples/s, 12 bit, external reference, adc_clk = 7 mhz, biasprog = 0x747 346 1 a 500 ksamples/s, 12 bit, internal 1.25v reference, adc_clk = 7 mhz, biasprog = 0x747 354 1 a 10 ksamples/s, 12 bit, internal 1.25 v reference, warmup = 00b, adc_clk = 7 mhz, bia- sprog = 0x747 52 1 a 10 ksamples/s, 12 bit, internal 1.25 v reference, warmup = 01b, adc_clk = 7 mhz, bia- sprog = 0x747 50 1 a 10 ksamples/s, 12 bit, internal 1.25 v reference, warmup = 10b, adc_clk = 7 mhz, bia- sprog = 0x747 54 1 a input capacitance c adcin 2 pf input on resistance r adcin 1 m input rc filter resistance r adcfilt 10 k input rc filter/decoupling ca- pacitance c adcfilt 250 ff input bias current i adcbiasin vss < vin < vdd -40 40 na EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 58 parameter symbol test condition min typ max unit input offset current i adcoffsetin vss < vin < vdd -40 40 na adc clock frequency f adcclk biasprog=0x747 7 mhz biasprog=0xf4b 13 mhz conversion time t adcconv 6 bit 7 adcclk cycles 8 bit 11 adcclk cycles 12 bit 13 adcclk cycles acquisition time t adcacq programmable 1 256 adcclk cycles required acquisition time for vdd/3 reference t adcacqvdd3 2 s startup time of reference gener- ator and adc core t adcstart normal mode 5 s keepadcwarm mode 1 s EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 59 parameter symbol test condition min typ max unit signal-to-noise ratio (snr) snr adc 1 msamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 13 mhz, biasprog = 0xf4b 59 db 1 msamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 63 db 1 msamples/s, 12 bit, single- ended, v dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 67 db 1 msamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 63 db 1 msamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 66 db 1 msamples/s, 12 bit, differen- tial, 5 v reference, adc_clk =13 mhz, biasprog = 0xf4b 66 db 1 msamples/s, 12 bit, differen- tial, v dd reference, adc_clk= 13 mhz, biasprog =0xf4b 63 69 db 1 msamples/s, 12 bit, differen- tial, 2xv dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 70 db 200 ksamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 7 mhz, bia- sprog = 0x747 62 db 200 ksamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 63 db 200 ksamples/s, 12 bit, single- ended, v dd reference, adc_clk = 7 mhz, bia- sprog = 0x747 67 db 200 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 63 db 200 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 66 db 200 ksamples/s, 12 bit, differen- tial, 5 v reference, adc_clk = 7 mhz, biasprog = 0x747 66 db EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 60 parameter symbol test condition min typ max unit signal-to-noise ratio (snr) snr adc 200 ksamples/s, 12 bit, differen- tial, v dd reference,adc_clk = 7 mhz, biasprog = 0x747 63 69 db 200 ksamples/s, 12 bit, differen- tial, 2xv dd reference,adc_clk = 7 mhz, biasprog = 0x747 70 db EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 61 parameter symbol test condition min typ max unit signal-to-noise and distortion ratio (sinad) sinad adc 1 msamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 13 mhz, biasprog = 0xf4b 58 db 1 msamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 62 db 1 msamples/s, 12 bit, single- ended, v dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 66 db 1 msamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 63 db 1 msamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 66 db 1 msamples/s, 12 bit, differen- tial, 5 v reference, adc_clk = 13 mhz, biasprog = 0xf4b 66 db 1 msamples/s, 12 bit, differen- tial, v dd reference, adc_clk = 13 mhz, biasprog = 0xf4b 62 68 db 1 msamples/s, 12 bit, differen- tial, 2xv dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 68 db 200 ksamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 7 mhz, bia- sprog = 0x747 61 db 200 ksamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 62 db 200 ksamples/s, 12 bit, single- ended, vdd reference, adc_clk = 7 mhz, bia- sprog = 0x747 66 db 200 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 63 db 200 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 66 db 200 ksamples/s, 12 bit, differen- tial, 5v reference, adc_clk= 7 mhz, biasprog = 0x747 66 db EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 62 parameter symbol test condition min typ max unit signal-to-noise and distortion ratio (sinad) sinad adc 200 ksamples/s, 12 bit, differen- tial, v dd reference, adc_clk = 7 mhz, biasprog = 0x747 62 68 db 200 ksamples/s, 12 bit, differen- tial, 2xv dd reference, adc_clk = 7 mhz, bia- sprog = 0x747 69 db EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 63 parameter symbol test condition min typ max unit spurious-free dynamic range (sfdr) sfdr adc 1 msamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 13 mhz, biasprog = 0xf4b 75 dbc 1 msamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 76 dbc 1 msamples/s, 12 bit, single- ended, v dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 76 dbc 1 msamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 78 dbc 1 msamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 77 dbc 1 msamples/s, 12 bit, differen- tial, v dd reference, adc_clk= 13 mhz, biasprog = 0xf4b 76 dbc 1 msamples/s, 12 bit, differen- tial, 2xv dd reference, adc_clk = 13 mhz, bia- sprog = 0xf4b 68 79 dbc 1 msamples/s, 12 bit, differen- tial, 5 v reference, adc_clk =13 mhz, biasprog = 0xf4b 79 dbc 200 ksamples/s, 12 bit, single- ended, internal 1.25 v refer- ence, adc_clk = 7 mhz, bia- sprog = 0x747 75 dbc 200 ksamples/s, 12 bit, single- ended, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 75 dbc 200 ksamples/s, 12 bit, single- ended, v dd reference, adc_clk = 7 mhz, bia- sprog = 0x747 76 dbc 200 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 79 dbc 200 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference, adc_clk = 7 mhz, bia- sprog = 0x747 79 dbc 200 ksamples/s, 12 bit, differen- tial, 5 v reference, adc_clk = 7 mhz, biasprog = 0x747 78 dbc EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 64 parameter symbol test condition min typ max unit spurious-free dynamic range (sfdr) sfdr adc 200 ksamples/s, 12 bit, differen- tial, v dd reference, adc_clk = 7 mhz, biasprog = 0x747 68 79 dbc 200 ksamples/s, 12 bit, differen- tial, 2xv dd reference,adc_clk = 7 mhz, biasprog = 0x747 79 dbc offset voltage v adcoffset after calibration, single-ended 0.3 mv after calibration, differential -4 0.3 4 mv thermometer output gradient tgrad adcth -1.92 mv/c -6.3 adc co- des/c differential non-linearity (dnl) dnl adc v dd = 3.0 v, external 2.5 v ref- erence -1 0.7 4 lsb integral non-linearity (inl), end point method inl adc v dd = 3.0 v, external 2.5 v ref- erence 1.2 3 lsb missing codes mc adc 3 lsb gain error drift gain ed 1.25 v reference 0.01 2 0.033 3 %/c 2.5 v reference 0.01 2 0.03 3 %/c offset error drift offset ed 1.25 v reference 0.00 2 0.06 3 lsb/c 2.5 v reference 0.00 2 0.04 3 lsb/c vref voltage v ref 1.25 v reference 1.2 1.25 1.3 v 2.5 v reference 2.4 2.5 2.6 v vref voltage drift v ref_vdrift 1.25 v reference -12.4 2.9 18.2 mv/v 2.5 v reference, vdd > 2.5 v -24.6 5.7 35.2 mv/v vref temperature drift v ref_tdrift 1.25 v reference -132 272 677 v/c 2.5 v reference -231 545 1271 v/c vref current consumption i vref 1.25 v reference 67 114 a 2.5 v reference 55 82 a adc and dac vref matching v ref_match 1.25 v reference 99.85 % 2.5 v reference 100.01 % note: 1. includes required contribution from the voltage reference. 2. typical numbers given by abs(mean) / (85 - 25). 3. max number given by (abs(mean) + 3x stddev) / (85 - 25). the integral non-linearity (inl) and differential non-linearity parameters are explained in the following figures. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 65 ideal transfer curve digital output code analog input inl=|[(v d -v ss )/v lsbideal ] - d| where 0 < d < 2 n - 1 0 1 2 3 4092 4093 4094 4095 v offset actual adc tranfer function before offset and gain correction actual adc tranfer function after offset and gain correction inl error (end point inl) figure 4.27. integral non-linearity (inl) ideal transfer curve digital output code analog input dnl=|[(v d+1 - v d )/v lsbideal ] - 1| where 0 < d < 2 n - 2 0 1 2 3 4092 4093 4094 4095 actual transfer function with one missing code. 4 5 full scale range 0.5 lsb ideal code center ideal 50% transition point ideal spacing between two adjacent codes v lsbideal =1 lsb code width =2 lsb dnl=1 lsb example: adjacent input value v d+1 corrresponds to digital output code d+1 example: input value v d corrresponds to digital output code d figure 4.28. differential non-linearity (dnl) EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 66 4.10.1 typical performance 1.25v reference 2.5v reference 2xvddvss reference 5vdiff reference vdd reference figure 4.29. adc frequency spectrum, vdd = 3v, temp = 25c EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 67 1.25v reference 2.5v reference 2xvddvss reference 5vdiff reference vdd reference figure 4.30. adc integral linearity error vs code, vdd = 3v, temp = 25c EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 68 1.25v reference 2.5v reference 2xvddvss reference 5vdiff reference vdd reference figure 4.31. adc differential linearity error vs code, vdd = 3v, temp = 25c EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 69 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 vdd (v) C4 C3 C2 C1 0 1 2 3 4 5 actual offset [lsb] vref=1v25 vref=2v5 vref=2xvddvss vref=5vdiff vref=vdd offset vs supply voltage, temp = 25c C40 C15 5 25 45 65 85 temp (c) C1.0 C0.5 0.0 0.5 1.0 1.5 2.0 actual offset [lsb] vref=1v25 vref=2v5 vref=2xvddvss vref=5vdiff vref=vdd offset vs temperature, vdd = 3v figure 4.32. adc absolute offset, common mode = vdd/2 C40 C15 5 25 45 65 85 temperature [c] 78.0 78.2 78.4 78.6 78.8 79.0 79.2 79.4 sfdr [db] 1v25 2v5 vdd 5vdiff 2xvddvss C40 C15 5 25 45 65 85 temperature [c] 63 64 65 66 67 68 69 70 71 snr [db] 1v25 2v5 vdd 5vdiff 2xvddvss signal to noise ratio (snr) spurious-free dynamic range (sfdr) figure 4.33. adc dynamic performance vs temperature for all adc references, vdd = 3v EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 70 4.11 digital analog converter (dac) table 4.15. dac parameter symbol test condition min typ max unit output voltage range v dacout vdd voltage reference, single- ended 0 v dd v vdd voltage reference, differen- tial -v dd v dd v output common mode voltage range v daccm 0 v dd v average active current i dac 500 ksamples/s, 12 bit, internal 1.25 v reference, continuous mode 400 1 650 1 a 100 ksamples/s, 12 bit, internal 1.25 v reference, sample/hold mode 200 1 250 1 a 1 ksamples/s 12 bit, internal 1.25 v reference, sample/off mode 17 1 25 1 a sample rate sr dac 500 ksamples/s dac clock frequency f dac continuous mode 1000 khz sample/hold mode 250 khz sample/off mode 250 khz clock cycles per conversion cyc dacconv 2 cycles conversion time t dacconv 2 s settling time t dacsettle 5 s signal-to-noise ratio (snr) snr dac 500 ksamples/s, 12 bit, single- ended, internal 1.25 v reference 58 db 500 ksamples/s, 12 bit, single- ended, internal 2.5 v reference 59 db 500 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference 58 db 500 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference 58 db 500 ksamples/s, 12 bit, differen- tial, v dd reference 59 db EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 71 parameter symbol test condition min typ max unit signal-to-noise plus distortion ratio (sndr) sndr dac 500 ksamples/s, 12 bit, single- ended, internal 1.25 v reference 57 db 500 ksamples/s, 12 bit, single- ended, internal 2.5 v reference 54 db 500 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference 56 db 500 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference 53 db 500 ksamples/s, 12 bit, differen- tial, v dd reference 55 db spurious-free dynamic range (sfdr) sfdr dac 500 ksamples/s, 12 bit, single- ended, internal 1.25v reference 62 dbc 500 ksamples/s, 12 bit, single- ended, internal 2.5 v reference 56 dbc 500 ksamples/s, 12 bit, differen- tial, internal 1.25 v reference 61 dbc 500 ksamples/s, 12 bit, differen- tial, internal 2.5 v reference 55 dbc 500 ksamples/s, 12 bit, differen- tial, v dd reference 60 dbc offset voltage v dacoffset after calibration, single-ended 2 mv after calibration, differential 2 mv sample-hold mode voltage drift v dacshmdrift 540 v/ms differential non-linearity dnl dac 1 lsb integral non-linearity inl dac 5 lsb no missing codes mc dac 12 bits load current i load_dc 11 ma vref voltage v ref 1.25 v reference 1.2 1.25 1.3 v 2.5 v reference 2.4 2.5 2.6 v vref voltage drift v ref_vdrift 1.25 v reference -12.4 2.9 18.2 mv/v 2.5 v reference, vdd > 2.5 v -24.6 5.7 35.2 mv/v vref temperature drift v ref_tdrift 1.25 v reference -132 272 677 v/c 2.5 v reference -231 545 1271 v/c vref current consumption i vref 1.25 v reference 67 114 a 2.5 v reference 55 82 a adc and dac vref matching v ref_match 1.25 v reference 99.85 % 2.5 v reference 100.01 % note: 1. measured with a static input code and no loading on the output. includes required contribution from the voltage reference. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 72 4.12 analog comparator (acmp) table 4.16. acmp parameter symbol test condition min typ max unit input voltage range v acmpin 0 v dd v acmp common mode voltage range v acmpcm 0 v dd v active current i acmp biasprog=0b0000, full- bias=0 and halfbias=1 in acmpn_ctrl register 55 600 a biasprog=0b1111, full- bias=0 and halfbias=0 in acmpn_ctrl register 2.82 12 a biasprog=0b1111, full- bias=1 and halfbias=0 in acmpn_ctrl register 250 520 a current consumption of internal voltage reference i acmpref internal voltage reference off. using external voltage refer- ence 0 0.5 a internal voltage reference, lpref=1 0.050 3 a internal voltage reference, lpref=0 6 a offset voltage v acmpoffset biasprog= 0b1010, full- bias=0 and halfbias=0 in acmpn_ctrl register -12 0 12 mv acmp hysteresis v acmphyst programmable 17 mv capacitive sense internal re- sistance r csres csressel=0b00 in acmpn_inputsel 39 k csressel=0b01 in acmpn_inputsel 71 k csressel=0b10 in acmpn_inputsel 104 k csressel=0b11 in acmpn_inputsel 136 k startup time t acmpstart 10 s the total acmp current is the sum of the contributions from the acmp and its internal voltage reference as given in the following equa- tion. i acmpref is zero if an external voltage reference is used. i acmptotal = i acmp + i acmpref EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 73 0 2 4 6 8 10 12 14 acmp_ctrl_biasprog 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 response time [us] hystsel=0.0 hystsel=2.0 hystsel=4.0 hystsel=6.0 0 1 2 3 4 5 6 7 acmp_ctrl_hystsel 0 20 40 60 80 100 hysteresis [mv] biasprog=0.0 biasprog=4.0 biasprog=8.0 biasprog=12.0 0 4 8 12 acmp_ctrl_biasprog 0.0 0.5 1.0 1.5 2.0 2.5 current [ua] current consumption, hystsel = 4 response time hysteresis figure 4.34. acmp characteristics, vdd = 3v, temp = 25c, fullbias = 0, halfbias = 1 EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 74 4.13 voltage comparator (vcmp) table 4.17. vcmp parameter symbol test condition min typ max unit input voltage range v vcmpin v dd v vcmp common mode voltage range v vcmpcm v dd v active current i vcmp biasprog=0b0000 and half- bias=1 in vcmpn_ctrl regis- ter 0.3 1 a biasprog=0b1111 and half- bias=0 in vcmpn_ctrl regis- ter. lpref=0. 22 30 a startup time reference genera- tor t vcmpref normal 10 s offset voltage v vcmpoffset single-ended 10 mv differential 10 mv vcmp hysteresis v vcmphyst 40 mv startup time t vcmpstart 10 s the v dd trigger level can be configured by setting the triglevel field of the vcmp_ctrl register in accordance with the following equation: v dd trigger level = 1.667 v + 0.034 triglevel EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 75 4.14 lcd table 4.18. lcd parameter symbol test condition min typ max unit frame rate f lcdfr 30 200 hz number of segments supported num seg 440 seg lcd supply voltage range v lcd internal boost circuit enabled 2.0 3.8 v steady state current consumption. i lcd display disconnected, static mode, framerate 32 hz, all segments on. 250 na display disconnected, quadruplex mode, framerate 32 hz, all seg- ments on, bias mode to one- third in lcd_dispctrl regis- ter. 550 na steady state current contribution of internal boost. i lcdboost internal voltage boost off 0 a internal voltage boost on, boosting from 2.2 v to 3.0 v. 8.4 a boost voltage v boost vblev of lcd_dispctrl regis- ter to level0 3.0 v vblev of lcd_dispctrl regis- ter to level1 3.08 v vblev of lcd_dispctrl regis- ter to level2 3.17 v vblev of lcd_dispctrl regis- ter to level3 3.26 v vblev of lcd_dispctrl regis- ter to level4 3.34 v vblev of lcd_dispctrl regis- ter to level5 3.43 v vblev of lcd_dispctrl regis- ter to level6 3.52 v vblev of lcd_dispctrl regis- ter to level7 3.6 v the total lcd current is given by the following equation. i lcdboost is zero if internal boost is off. i lcdtotal = i lcd + i lcdboost EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 76 4.15 i2c table 4.19. i2c standard-mode (sm) parameter symbol min typ max unit scl clock frequency f scl 0 100 1 khz scl clock low time t low 4.7 s scl clock high time t high 4.0 s sda set-up time t su,dat 250 ns sda hold time t hd,dat 8 3450 2,3 ns repeated start condition set-up time t su,sta 4.7 s (repeated) start condition hold time t hd,sta 4.0 s stop condition set-up time t su,sto 4.0 s bus free time between a stop and a start condition t buf 4.7 s note: 1. for the minimum hfperclk frequency required in standard-mode, see the i2c chapter in the EFM32G reference manual. 2. the maximum sda hold time (t hd,dat ) needs to be met only when the device does not stretch the low time of scl (t low ). 3. when transmitting data, this number is guaranteed only when i2cn_clkdiv < ((3450*10 -9 [s] * f hfperclk [hz]) - 4). table 4.20. i2c fast-mode (fm) parameter symbol min typ max unit scl clock frequency f scl 0 400 1 khz scl clock low time t low 1.3 s scl clock high time t high 0.6 s sda set-up time t su,dat 100 ns sda hold time t hd,dat 8 900 2,3 ns repeated start condition set-up time t su,sta 0.6 s (repeated) start condition hold time t hd,sta 0.6 s stop condition set-up time t su,sto 0.6 s bus free time between a stop and a start condition t buf 1.3 s note: 1. for the minimum hfperclk frequency required in fast-mode, see the i2c chapter in the EFM32G reference manual. 2. the maximum sda hold time (t hd,dat ) needs to be met only when the device does not stretch the low time of scl (t low ). 3. when transmitting data, this number is guaranteed only when i2cn_clkdiv < ((900*10 -9 [s] * f hfperclk [hz]) - 4). EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 77 table 4.21. i2c fast-mode plus (fm+) parameter symbol min typ max unit scl clock frequency f scl 0 1000 1 khz scl clock low time t low 0.5 s scl clock high time t high 0.26 s sda set-up time t su,dat 50 ns sda hold time t hd,dat 8 ns repeated start condition set-up time t su,sta 0.26 s (repeated) start condition hold time t hd,sta 0.26 s stop condition set-up time t su,sto 0.26 s bus free time between a stop and a start condition t buf 0.5 s note: 1. for the minimum hfperclk frequency required in fast-mode plus, see the i2c chapter in the EFM32G reference manual. 4.16 digital peripherals table 4.22. digital peripherals parameter symbol test condition min typ max unit usart current i usart usart idle current, clock enabled 7.5 a/mhz uart current i uart uart idle current, clock enabled 5.63 a/mhz leuart current i leuart leuart idle current, clock enabled 150 na i2c current i i2c i2c idle current, clock enabled 6.25 a/mhz timer current i timer timer_0 idle current, clock enabled 8.75 a/mhz letimer current i letimer letimer idle current, clock enabled 150 na pcnt current i pcnt pcnt idle current, clock enabled 100 na rtc current i rtc rtc idle current, clock enabled 100 na lcd current i lcd lcd idle current, clock enabled 100 na aes current i aes aes idle current, clock enabled 2.5 a/mhz gpio current i gpio gpio idle current, clock enabled 5.31 a/mhz ebi current i ebi ebi idle current, clock enabled 1.56 a/mhz prs current i prs prs idle current 2.81 a/mhz dma current i dma clock enable 8.12 a/mhz note: please refer to the application note "an0002 efm32 hardware design considerations" forguidelines on designing printed circuit boards (pcb's) for the EFM32G. EFM32G data sheet electrical characteristics silabs.com | building a more connected world. rev. 2.10 | 78 5. pin definitions note: please refer to the application note "an0002 efm32 hardware design considerations" for guidelines on designing printed cir- cuit boards (pcbs) for the EFM32G. 5.1 EFM32G200 & EFM32G210 (qfn32) 5.1.1 pinout the EFM32G200 and EFM32G210 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location number (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bit- field in the *_route register in the module in question. figure 5.1. EFM32G200 & EFM32G210 pinout (top view, not to scale) EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 79 table 5.1. device pinout qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vss ground. 1 pa0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 tim0_cc2 #0/1 cmu_clk0 #0 4 iovdd_1 digital io power supply 1. 5 pc0 acmp0_ch0 pcnt0_s0in #2 us1_tx #0 6 pc1 acmp0_ch1 pcnt0_s1in #2 us1_rx #0 7 pb7 lfxtal_p us1_clk #0 8 pb8 lfxtal_n us1_cs #0 9 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 10 pb11 dac0_out0 letim0_out0 #1 11 avdd_2 analog power supply 2. 12 pb13 hfxtal_p leu0_tx #1 13 pb14 hfxtal_n leu0_rx #1 14 iovdd_3 digital io power supply 3. 15 avdd_0 analog power supply 0. 16 pd4 adc0_ch4 leu0_tx #0 17 pd5 adc0_ch5 leu0_rx #0 18 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 19 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 20 vdd_dreg power supply for on-chip voltage regulator. 21 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 22 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 23 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 24 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 25 pf0 letim0_out0 #2 dbg_swclk #0/1 26 pf1 letim0_out1 #2 dbg_swdio #0/1 27 pf2 acmp1_o #0 dbg_swo #0 28 iovdd_5 digital io power supply 5. 29 pe10 tim1_cc0 #1 us0_tx #0 boot_tx 30 pe11 tim1_cc1 #1 us0_rx #0 boot_rx EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 80 qfn32 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 31 pe12 tim1_cc2 #1 us0_clk #0 32 pe13 us0_cs #0 acmp0_o #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 81 5.1.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.2. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 clock management unit, clock output number 0. cmu_clk1 pa1 clock management unit, clock output number 1. dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 low energy timer letim0, output channel 0. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 82 alternate location functionality 0 1 2 3 description letim0_out1 pd7 pf1 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 leuart0 receive input. leu0_tx pd4 pb13 leuart0 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pc1 pulse counter pcnt0 input number 1. tim0_cc0 pa0 pa0 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 timer 0 capture compare input / output channel 2. tim0_cdti0 pc13 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pc14 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pc15 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. us0_clk pe12 usart0 clock input / output. us0_cs pe13 usart0 chip select input / output. us0_rx pe11 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 usart1 clock input / output. us1_cs pb8 usart1 chip select input / output. us1_rx pc1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 83 5.1.3 gpio pinout overview the specific gpio pins available in EFM32G200 and EFM32G210 is shown in the following table. each gpio port is organized as 16- bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.3. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa2 pa1 pa0 port b pb14 pb13 pb11 pb8 pb7 port c pc15 pc14 pc13 pc1 pc0 port d pd7 pd6 pd5 pd4 port e pe13 pe12 pe11 pe10 port f pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 84 5.2 EFM32G222 (tqfp48) 5.2.1 pinout the EFM32G222 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.2. EFM32G222 pinout (top view, not to scale) table 5.4. device pinout tqfp48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 1 pa0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 tim0_cc2 #0/1 cmu_clk0 #0 4 iovdd_0 digital io power supply 0. 5 vss ground. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 85 tqfp48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 6 pc0 acmp0_ch0 pcnt0_s0in #2 us1_tx #0 7 pc1 acmp0_ch1 pcnt0_s1in #2 us1_rx #0 8 pc2 acmp0_ch2 9 pc3 acmp0_ch3 10 pc4 acmp0_ch4 letim0_out0 #3 pcnt1_s0in #0 11 pb7 lfxtal_p us1_clk #0 12 pb8 lfxtal_n us1_cs #0 13 pa8 tim2_cc0 #0 14 pa9 tim2_cc1 #0 15 pa10 tim2_cc2 #0 16 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 17 pb11 dac0_out0 letim0_out0 #1 18 vss ground. 19 avdd_1 analog power supply 1. 20 pb13 hfxtal_p leu0_tx #1 21 pb14 hfxtal_n leu0_rx #1 22 iovdd_3 digital io power supply 3. 23 avdd_0 analog power supply 0. 24 pd4 adc0_ch4 leu0_tx #0 25 pd5 adc0_ch5 leu0_rx #0 26 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 27 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 28 vdd_dreg power supply for on-chip voltage regulator. 29 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 30 pc8 acmp1_ch0 tim2_cc0 #2 us0_cs #2 31 pc9 acmp1_ch1 tim2_cc1 #2 us0_clk #2 32 pc10 acmp1_ch2 tim2_cc2 #2 us0_rx #2 33 pc11 acmp1_ch3 us0_tx #2 34 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 35 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 36 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 37 pf0 letim0_out0 #2 dbg_swclk #0/1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 86 tqfp48 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 38 pf1 letim0_out1 #2 dbg_swdio #0/1 39 pf2 acmp1_o #0 dbg_swo #0 40 pf3 tim0_cdti0 #2 41 pf4 tim0_cdti1 #2 42 pf5 tim0_cdti2 #2 43 iovdd_5 digital io power supply 5. 44 vss ground. 45 pe10 tim1_cc0 #1 us0_tx #0 boot_tx 46 pe11 tim1_cc1 #1 us0_rx #0 boot_rx 47 pe12 tim1_cc2 #1 us0_clk #0 48 pe13 us0_cs #0 acmp0_o #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 87 5.2.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.5. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 clock management unit, clock output number 0. cmu_clk1 pa1 clock management unit, clock output number 1. dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 88 alternate location functionality 0 1 2 3 description dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pf1 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 leuart0 receive input. leu0_tx pd4 pb13 leuart0 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pulse counter pcnt1 input number 0. tim0_cc0 pa0 pa0 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 timer 0 capture compare input / output channel 2. tim0_cdti0 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. tim2_cc0 pa8 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pc10 timer 2 capture compare input / output channel 2. us0_clk pe12 pc9 usart0 clock input / output. us0_cs pe13 pc8 usart0 chip select input / output. us0_rx pe11 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 89 alternate location functionality 0 1 2 3 description us0_tx pe10 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 usart1 clock input / output. us1_cs pb8 usart1 chip select input / output. us1_rx pc1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). 5.2.3 gpio pinout overview the specific gpio pins available in EFM32G222 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.6. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa10 pa9 pa8 pa2 pa1 pa0 port b pb14 pb13 pb11 pb8 pb7 port c pc15 pc14 pc13 pc11 pc10 pc9 pc8 pc4 pc3 pc2 pc1 pc0 port d pd7 pd6 pd5 pd4 port e pe13 pe12 pe11 pe10 port f pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 90 5.3 EFM32G230 (qfn64) 5.3.1 pinout the EFM32G230 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.3. EFM32G230 pinout (top view, not to scale) table 5.7. device pinout qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vss ground. 1 pa0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 tim0_cc2 #0/1 cmu_clk0 #0 4 pa3 tim0_cdti0 #0 5 pa4 tim0_cdti1 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 91 qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 6 pa5 tim0_cdti2 #0 leu1_tx #1 6 pa6 leu1_rx #1 8 iovdd_0 digital io power supply 0. 9 pc0 pcnt0_s0in #1 us1_tx #0 10 pc1 pcnt0_s1in #1 us1_rx #0 11 pc2 us2_clk #0 12 pc3 us2_cs #0 13 pc4 acmp0_ch4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 14 pc5 acmp0_ch5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 15 pb7 lfxtal_p us1_clk #0 16 pb8 lfxtal_n us1_cs #0 17 pa8 tim2_cc0 #0 18 pa9 tim2_cc1 #0 19 pa10 tim2_cc2 #0 20 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 21 pb11 dac0_out0 letim0_out0 #1 22 pb12 dac0_out1 letim0_out1 #1 23 avdd_1 analog power supply 1. 24 pb13 hfxtal_p leu0_tx #1 25 pb14 hfxtal_n leu0_rx #1 26 iovdd_3 digital io power supply 3. 27 avdd_0 analog power supply 0. 28 pd0 adc0_ch0 pcnt2_s0in #0 us1_tx #1 29 pd1 adc0_ch1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 30 pd2 adc0_ch2 tim0_cc1 #3 us1_clk #1 31 pd3 adc0_ch3 tim0_cc2 #3 us1_cs #1 32 pd4 adc0_ch4 leu0_tx #0 33 pd5 adc0_ch5 leu0_rx #0 34 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 35 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 36 pd8 cmu_clk1 #1 37 pc6 acmp0_ch6 leu1_tx #0 i2c0_sda #2 38 pc7 acmp0_ch7 leu1_rx #0 i2c0_scl #2 39 vdd_dreg power supply for on-chip voltage regulator. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 92 qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 40 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 41 pc8 acmp1_ch0 tim2_cc0 #2 us0_cs #2 42 pc9 acmp1_ch1 tim2_cc1 #2 us0_clk #2 43 pc10 acmp1_ch2 tim2_cc2 #2 us0_rx #2 44 pc11 acmp1_ch3 us0_tx #2 45 pc12 acmp1_ch4 cmu_clk0 #1 46 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 47 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 48 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 49 pf0 letim0_out0 #2 dbg_swclk #0/1 50 pf1 letim0_out1 #2 dbg_swdio #0/1 51 pf2 acmp1_o #0 dbg_swo #0 52 pf3 tim0_cdti0 #2 53 pf4 tim0_cdti1 #2 54 pf5 tim0_cdti2 #2 55 iovdd_5 digital io power supply 5. 56 pe8 pcnt2_s0in #1 57 pe9 pcnt2_s1in #1 58 pe10 tim1_cc0 #1 us0_tx #0 boot_tx 59 pe11 tim1_cc1 #1 us0_rx #0 boot_rx 60 pe12 tim1_cc2 #1 us0_clk #0 61 pe13 us0_cs #0 acmp0_o #0 62 pe14 leu0_tx #2 63 pe15 leu0_rx #2 64 pa15 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 93 5.3.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.8. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp2, channel 1. acmp1_ch2 pc10 analog comparator acmp3, channel 2. acmp1_ch3 pc11 analog comparator acmp4, channel 3. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 94 alternate location functionality 0 1 2 3 description dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 95 alternate location functionality 0 1 2 3 description tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. tim2_cc0 pa8 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pc10 timer 2 capture compare input / output channel 2. us0_clk pe12 pc9 usart0 clock input / output. us0_cs pe13 pc8 usart0 chip select input / output. us0_rx pe11 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 usart2 clock input / output. us2_cs pc5 usart2 chip select input / output. us2_rx pc3 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 96 5.3.3 gpio pinout overview the specific gpio pins available in EFM32G230 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.9. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa10 pa8 pa8 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb12 pb11 pb8 pb7 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 port f pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 97 5.4 EFM32G232 (tqfp64) 5.4.1 pinout the EFM32G232 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.4. EFM32G232 pinout (top view, not to scale) table 5.10. device pinout tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 1 pa0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 tim0_cc2 #0/1 cmu_clk0 #0 4 pa3 tim0_cdti0 #0 5 pa4 tim0_cdti1 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 98 tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 6 pa5 tim0_cdti2 #0 leu1_tx #1 7 iovdd_0 digital io power supply 0. 8 vss ground. 9 pc0 acmp0_ch0 pcnt0_s0in #1 us1_tx #1 10 pc1 acmp0_ch1 pcnt0_s1in #1 us1_rx #1 11 pc2 acmp0_ch2 us1_clk #1 12 pc3 acmp0_ch3 us1_cs #1 13 pc4 acmp0_ch4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 14 pc5 acmp0_ch5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 15 pb7 lfxtal_p us1_clk #0 16 pb8 lfxtal_n us1_cs #0 17 pa8 tim2_cc0 #0 18 pa9 tim2_cc1 #0 19 pa10 tim2_cc2 #0 20 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 21 pb11 dac0_out0 letim0_out0 #1 22 vss ground. 23 avdd_1 analog power supply 1. 24 pb13 hfxtal_p leu0_tx #1 25 pb14 hfxtal_n leu0_rx #1 26 iovdd_3 digital io power supply 3. 27 avdd_0 analog power supply 0. 28 pd0 adc0_ch0 pcnt2_s0in #0 us1_tx #1 29 pd1 adc0_ch1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 30 pd2 adc0_ch2 tim0_cc1 #3 us1_clk #1 31 pd3 adc0_ch3 tim0_cc2 #3 us1_cs #1 32 pd4 adc0_ch4 leu0_tx #0 33 pd5 adc0_ch5 leu0_rx #0 34 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 35 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 36 pd8 cmu_clk1 #1 37 pc6 acmp0_ch6 leu1_tx #0 i2c0_sda #2 38 pc7 acmp0_ch7 leu1_rx #0 i2c0_scl #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 99 tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 39 vdd_dreg power supply for on-chip voltage regulator. 40 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 41 pc8 acmp1_ch0 tim2_cc0 #2 us0_cs #2 42 pc9 acmp1_ch1 tim2_cc1 #2 us0_clk #2 43 pc10 acmp1_ch2 tim2_cc2 #2 us0_rx #2 44 pc11 acmp1_ch3 us0_tx #2 45 pc12 acmp1_ch4 cmu_clk0 #1 46 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 47 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 48 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 49 pf0 letim0_out0 #2 dbg_swclk #0/1 50 pf1 letim0_out1 #2 dbg_swdio #0/1 51 pf2 acmp1_o #0 dbg_swo #0 52 pf3 tim0_cdti0 #2 53 pf4 tim0_cdti1 #2 54 pf5 tim0_cdti2 #2 55 iovdd_5 digital io power supply 5. 56 vss ground. 57 pe8 pcnt2_s0in #1 58 pe9 pcnt2_s1in #1 59 pe10 tim1_cc0 #1 us0_tx #0 boot_tx 60 pe11 tim1_cc1 #1 us0_rx #0 boot_rx 61 pe12 tim1_cc2 #1 us0_clk #0 62 pe13 us0_cs #0 acmp0_o #0 63 pe14 leu0_tx #2 64 pe15 leu0_rx #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 100 5.4.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.11. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch4 pc0 analog comparator acmp0, channel 0. acmp0_ch5 pc1 analog comparator acmp0, channel 1. acmp0_ch6 pc2 analog comparator acmp0, channel 2. acmp0_ch7 pc3 analog comparator acmp0, channel 3. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 101 alternate location functionality 0 1 2 3 description dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. tim2_cc0 pa8 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pc10 timer 2 capture compare input / output channel 2. us0_clk pe12 pc9 usart0 clock input / output. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 102 alternate location functionality 0 1 2 3 description us0_cs pe13 pc8 usart0 chip select input / output. us0_rx pe11 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 usart2 clock input / output. us2_cs pc5 usart2 chip select input / output. us2_rx pc3 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). 5.4.3 gpio pinout overview the specific gpio pins available in EFM32G2322 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.12. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa10 pa9 pa8 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb11 pb8 pb7 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 port f pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 103 5.5 EFM32G280 (lqfp100) 5.5.1 pinout the EFM32G280 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.5. EFM32G280 pinout (top view, not to scale) table 5.13. device pinout lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 1 pa0 ebi_ad09 #0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 ebi_ad10 #0 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 ebi_ad11 #0 tim0_cc2 #0/1 cmu_clk0 #0 4 pa3 ebi_ad12 #0 tim0_cdti0 #0 u0_tx #2 5 pa4 ebi_ad13 #0 tim0_cdti1 #0 u0_rx #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 104 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 6 pa5 ebi_ad14 #0 tim0_cdti2 #0 leu1_tx #1 7 pa6 ebi_ad15 #0 leu1_rx #1 8 iovdd_0 digital io power supply 0. 9 pb0 tim1_cc0 #2 10 pb1 tim1_cc1 #2 11 pb2 tim1_cc2 #2 12 pb3 pcnt1_s0in #1 us2_tx #1 13 pb4 pcnt1_s1in #1 us2_rx #1 14 pb5 us2_clk #1 15 pb6 us2_cs #1 16 vss ground. 17 iovdd_1 digital io power supply 1. 18 pc0 acmp0_c h0 pcnt0_s0in #2 us1_tx #0 19 pc1 acmp0_c h1 pcnt0_s1in #2 us1_rx #0 20 pc2 acmp0_c h2 us2_tx #0 21 pc3 acmp0_c h3 us2_rx #0 22 pc4 acmp0_c h4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 23 pc5 acmp0_c h5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 24 pb7 lfxtal_p us1_clk #0 25 pb8 lfxtal_n us1_cs #0 26 pa7 27 pa8 tim2_cc0 #0 28 pa9 tim2_cc1 #0 29 pa10 tim2_cc2 #0 30 pa11 31 iovdd_2 digital io power supply 2. 32 vss ground. 33 pa12 tim2_cc0 #1 34 pa13 tim2_cc1 #1 35 pa14 tim2_cc2 #1 36 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 105 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 37 pb9 38 pb10 39 pb11 dac0_ou t0 letim0_out0 #1 40 pb12 dac0_ou t1 letim0_out1 #1 41 avdd_1 analog power supply 1. 42 pb13 hfxtal_ p leu0_tx #1 43 pb14 hfxtal_ n leu0_rx #1 44 iovdd_3 digital io power supply 3. 45 avdd_0 analog power supply 0. 46 pd0 adc0_ch 0 pcnt2_s0in #0 us1_tx #1 47 pd1 adc0_ch 1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 48 pd2 adc0_ch 2 tim0_cc1 #3 us1_clk #1 49 pd3 adc0_ch 3 tim0_cc2 #3 us1_cs #1 50 pd4 adc0_ch 4 leu0_tx #0 51 pd5 adc0_ch 5 leu0_rx #0 52 pd6 adc0_ch 6 letim0_out0 #0 i2c0_sda #1 53 pd7 adc0_ch 7 letim0_out1 #0 i2c0_scl #1 54 pd8 cmu_clk1 #1 55 pc6 acmp0_c h6 leu1_tx #0 i2c0_sda #2 56 pc7 acmp0_c h7 leu1_rx #0 i2c0_scl #2 57 vdd_dre g power supply for on-chip voltage regulator. 58 vss ground. 59 decou- ple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 60 pe0 pcnt0_s0in #1 u0_tx #1 61 pe1 pcnt0_s1in #1 u0_rx #1 62 pe2 acmp0_o #1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 106 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 63 pe3 acmp1_o #1 64 pe4 us0_cs #1 65 pe5 us0_clk #1 66 pe6 us0_rx #1 67 pe7 us0_tx #1 68 pc8 acmp1_c h0 tim2_cc0 #2 us0_cs #2 69 pc9 acmp1_c h1 tim2_cc1 #2 us0_clk #2 70 pc10 acmp1_c h2 tim2_cc2 #2 us0_rx #2 71 pc11 acmp1_c h3 us0_tx #2 72 pc12 acmp1_c h4 cmu_clk0 #1 73 pc13 acmp1_c h5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 74 pc14 acmp1_c h6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 u0_tx #3 75 pc15 acmp1_c h7 tim0_cdti2 #1/3 tim1_cc2 #0 u0_rx #3 dbg_swo #1 76 pf0 letim0_out0 #2 dbg_swclk #0/1 77 pf1 letim0_out1 #2 dbg_swdio #0/1 78 pf2 ebi_ardy #0 acmp1_o #0 dbg_swo #0 79 pf3 ebi_ale #0 tim0_cdti0 #2 80 pf4 ebi_wen #0 tim0_cdti1 #2 81 pf5 ebi_ren #0 tim0_cdti2 #2 82 iovdd_5 digital io power supply 5. 83 vss ground. 84 pf6 tim0_cc0 #2 u0_tx #0 85 pf7 tim0_cc1 #2 u0_rx #0 86 pf8 tim0_cc2 #2 87 pf9 88 pd9 ebi_cs0 #0 89 pd10 ebi_cs1 #0 90 pd11 ebi_cs2 #0 91 pd12 ebi_cs3 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 107 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 92 pe8 ebi_ad00 #0 pcnt2_s0in #1 93 pe9 ebi_ad01 #0 pcnt2_s1in #1 94 pe10 ebi_ad02 #0 tim1_cc0 #1 us0_tx #0 boot_tx 95 pe11 ebi_ad03 #0 tim1_cc1 #1 us0_rx #0 boot_rx 96 pe12 ebi_ad04 #0 tim1_cc2 #1 us0_clk #0 97 pe13 ebi_ad05 #0 us0_cs #0 acmp0_o #0 98 pe14 ebi_ad06 #0 leu0_tx #2 99 pe15 ebi_ad07 #0 leu0_rx #2 100 pa15 ebi_ad08 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 108 5.5.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.14. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 pe2 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 pe3 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 109 alternate location functionality 0 1 2 3 description dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. ebi_ad00 pe8 external bus interface (ebi) address and data input / output pin 00. ebi_ad01 pe9 external bus interface (ebi) address and data input / output pin 01. ebi_ad02 pe10 external bus interface (ebi) address and data input / output pin 02. ebi_ad03 pe11 external bus interface (ebi) address and data input / output pin 03. ebi_ad04 pe12 external bus interface (ebi) address and data input / output pin 04. ebi_ad05 pe13 external bus interface (ebi) address and data input / output pin 05. ebi_ad06 pe14 external bus interface (ebi) address and data input / output pin 06. ebi_ad07 pe15 external bus interface (ebi) address and data input / output pin 07. ebi_ad08 pa15 external bus interface (ebi) address and data input / output pin 08. ebi_ad09 pa0 external bus interface (ebi) address and data input / output pin 09. ebi_ad10 pa1 external bus interface (ebi) address and data input / output pin 10. ebi_ad11 pa2 external bus interface (ebi) address and data input / output pin 11. ebi_ad12 pa3 external bus interface (ebi) address and data input / output pin 12. ebi_ad13 pa4 external bus interface (ebi) address and data input / output pin 13. ebi_ad14 pa5 external bus interface (ebi) address and data input / output pin 14. ebi_ad15 pa6 external bus interface (ebi) address and data input / output pin 15. ebi_ale pf3 external bus interface (ebi) address latch enable output. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 110 alternate location functionality 0 1 2 3 description ebi_ardy pf2 external bus interface (ebi) hardware ready control input. ebi_cs0 pd9 external bus interface (ebi) chip select output 0. ebi_cs1 pd10 external bus interface (ebi) chip select output 1. ebi_cs2 pd11 external bus interface (ebi) chip select output 2. ebi_cs3 pd12 external bus interface (ebi) chip select output 3. ebi_ren pf5 external bus interface (ebi) read enable output. ebi_wen pf4 external bus interface (ebi) write enable output. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pe0 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pe1 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pf6 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pf7 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pf8 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 pb0 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 pb1 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 pb2 timer 1 capture compare input / output channel 2. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 111 alternate location functionality 0 1 2 3 description tim2_cc0 pa8 pa12 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pa13 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pa14 pc10 timer 2 capture compare input / output channel 2. u0_rx pf7 pe1 pa4 pc15 uart0 receive input. u0_tx pf6 pe0 pa3 pc14 uart0 transmit output. also used as receive input in half du- plex communication. us0_clk pe12 pe5 pc9 usart0 clock input / output. us0_cs pe13 pe4 pc8 usart0 chip select input / output. us0_rx pe11 pe6 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pc3 pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 112 5.5.3 gpio pinout overview the specific gpio pins available in EFM32G280 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.15. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port f pf9 pf8 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 113 5.6 EFM32G290 (bga112) 5.6.1 pinout the EFM32G290 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.6. EFM32G280 pinout (top view, not to scale) table 5.16. device pinout bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other a1 pe15 ebi_ad07 #0 leu0_rx #2 a2 pe14 ebi_ad06 #0 leu0_tx #2 a3 pe12 ebi_ad04 #0 tim1_cc2 #1 us0_clk #0 a4 pe9 ebi_ad01 #0 pcnt2_s1in #1 a5 pd10 ebi_cs1 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 114 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other a6 pf7 tim0_cc1 #2 u0_rx #0 a7 pf5 ebi_ren #0 tim0_cdti2 #2 a8 pf4 ebi_wen #0 tim0_cdti1 #2 a9 pe4 us0_cs #1 a10 pc14 acmp1_c h6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 u0_tx #3 a11 pc15 acmp1_c h7 tim0_cdti2 #1/3 tim1_cc2 #0 u0_rx #3 dbg_swo #1 b1 pa15 ebi_ad08 #0 b2 pe13 ebi_ad05 #0 us0_cs #0 acmp0_o #0 b3 pe11 ebi_ad03 #0 tim1_cc1 #1 us0_rx #0 boot_rx b4 pe8 ebi_ad00 #0 pcnt2_s0in #1 b5 pd11 ebi_cs2 #0 b6 pf8 tim0_cc2 #2 b7 pf6 tim0_cc0 #2 u0_tx #0 b8 pf3 ebi_ale #0 tim0_cdti0 #2 b9 pe5 us0_clk #1 b10 pc12 acmp1_c h4 cmu_clk0 #1 b11 pc13 acmp1_c h5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 c1 pa1 ebi_ad10 #0 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 c2 pa0 ebi_ad09 #0 tim0_cc0 #0/1 i2c0_sda #0 c3 pe10 ebi_ad02 #0 tim1_cc0 #1 us0_tx #0 boot_tx c4 pd13 c5 pd12 ebi_cs3 #0 c6 pf9 c7 vss ground. c8 pf2 ebi_ardy #0 acmp1_o #0 dbg_swo #0 c9 pe6 us0_rx #1 c10 pc10 acmp1_c h2 tim2_cc2 #2 us0_rx #2 c11 pc11 acmp1_c h3 us0_tx #2 d1 pa3 ebi_ad12 #0 tim0_cdti0 #0 u0_tx #2 d2 pa2 ebi_ad11 #0 tim0_cc2 #0/1 cmu_clk0 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 115 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other d3 pb15 d4 vss ground. d5 iovdd_6 digital io power supply 6. d6 pd9 lcd_seg 28 ebi_cs0 #0 d7 iovdd_5 digital io power supply 5. d8 pf1 letim0_out1 #2 dbg_swdio #0/1 d9 pe7 us0_tx #1 d10 pc8 acmp1_c h0 tim2_cc0 #2 us0_cs #2 d11 pc9 acmp1_c h1 tim2_cc1 #2 us0_clk #2 e1 pa6 ebi_ad15 #0 leu1_rx #1 e2 pa5 ebi_ad14 #0 tim0_cdti2 #0 leu1_tx #1 e3 pa4 ebi_ad13 #0 tim0_cdti1 #0 u0_rx #2 e4 pb0 tim1_cc0 #2 e8 pf0 letim0_out0 #2 dbg_swclk #0/1 e9 pe0 pcnt0_s0in #1 u0_tx #1 e10 pe1 pcnt0_s1in #1 u0_rx #1 e11 pe3 acmp1_o #1 f1 pb1 tim1_cc1 #2 f2 pb2 tim1_cc2 #2 f3 pb3 pcnt1_s0in #1 us2_tx #1 f4 pb4 pcnt1_s1in #1 us2_rx #1 f8 vdd_dre g power supply for on-chip voltage regulator. f9 vss_dre g ground for on-chip voltage regulator. f10 pe2 acmp0_o #1 f11 decou- ple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. g1 pb5 us2_clk #1 g2 pb6 us2_cs #1 g3 vss ground. g4 iovdd_0 digital io power supply 0. g8 iovdd_4 digital io power supply 4. g9 vss ground. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 116 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other g10 pc6 acmp0_c h6 leu1_tx #0 i2c0_sda #2 g11 pc7 acmp0_c h7 leu1_rx #0 i2c0_scl #2 h1 pc0 acmp0_c h0 pcnt0_s0in #2 us1_tx #0 h2 pc2 acmp0_c h2 us2_tx #0 h3 pd14 i2c0_sda #3 h4 pa7 h5 pa8 tim2_cc0 #0 h6 vss ground. h7 iovdd_3 digital io power supply 3. h8 pd8 cmu_clk1 #1 h9 pd5 adc0_ch 5 leu0_rx #0 h10 pd6 adc0_ch 6 letim0_out0 #0 i2c0_sda #1 h11 pd7 adc0_ch 7 letim0_out1 #0 i2c0_scl #1 j1 pc1 acmp0_c h1 pcnt0_s1in #2 us1_rx #0 j2 pc3 acmp0_c h3 us2_rx #0 j3 pd15 i2c0_scl #3 j4 pa12 tim2_cc0 #1 j5 pa9 tim2_cc1 #0 j6 pa10 tim2_cc2 #0 j7 pb9 j8 pb10 j9 pd2 adc0_ch 2 tim0_cc1 #3 us1_clk #1 j10 pd3 adc0_ch 3 tim0_cc2 #3 us1_cs #1 j11 pd4 adc0_ch 4 leu0_tx #0 k1 pb7 lfxtal_p us1_clk #0 k2 pc4 acmp0_c h4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 k3 pa13 tim2_cc1 #1 k4 vss ground. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 117 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other k5 pa11 k6 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. k7 avss_1 analog ground 1. k8 avdd_2 analog power supply 2. k9 avdd_1 analog power supply 1. k10 avss_0 analog ground 0. k11 pd1 adc0_ch 1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 l1 pb8 lfxtal_n us1_cs #0 l2 pc5 acmp0_c h5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 l3 pa14 tim2_cc2 #1 l4 iovdd_1 digital io power supply 1. l5 pb11 dac0_ou t0 letim0_out0 #1 l6 pb12 dac0_ou t1 letim0_out1 #1 l7 avss_2 analog ground 2. l8 pb13 hfxtal_ p leu0_tx #1 l9 pb14 hfxtal_ n leu0_rx #1 l10 avdd_0 analog power supply 0. l11 pd0 adc0_ch 0 pcnt2_s0in #0 us1_tx #1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 118 5.6.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.17. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 pe2 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 pe3 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 119 alternate location functionality 0 1 2 3 description dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. ebi_ad00 pe8 external bus interface (ebi) address and data input / output pin 00. ebi_ad01 pe9 external bus interface (ebi) address and data input / output pin 01. ebi_ad02 pe10 external bus interface (ebi) address and data input / output pin 02. ebi_ad03 pe11 external bus interface (ebi) address and data input / output pin 03. ebi_ad04 pe12 external bus interface (ebi) address and data input / output pin 04. ebi_ad05 pe13 external bus interface (ebi) address and data input / output pin 05. ebi_ad06 pe14 external bus interface (ebi) address and data input / output pin 06. ebi_ad07 pe15 external bus interface (ebi) address and data input / output pin 07. ebi_ad08 pa15 external bus interface (ebi) address and data input / output pin 08. ebi_ad09 pa0 external bus interface (ebi) address and data input / output pin 09. ebi_ad10 pa1 external bus interface (ebi) address and data input / output pin 10. ebi_ad11 pa2 external bus interface (ebi) address and data input / output pin 11. ebi_ad12 pa3 external bus interface (ebi) address and data input / output pin 12. ebi_ad13 pa4 external bus interface (ebi) address and data input / output pin 13. ebi_ad14 pa5 external bus interface (ebi) address and data input / output pin 14. ebi_ad15 pa6 external bus interface (ebi) address and data input / output pin 15. ebi_ale pf3 external bus interface (ebi) address latch enable output. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 120 alternate location functionality 0 1 2 3 description ebi_ardy pf2 external bus interface (ebi) hardware ready control input. ebi_cs0 pd9 external bus interface (ebi) chip select output 0. ebi_cs1 pd10 external bus interface (ebi) chip select output 1. ebi_cs2 pd11 external bus interface (ebi) chip select output 2. ebi_cs3 pd12 external bus interface (ebi) chip select output 3. ebi_ren pf5 external bus interface (ebi) read enable output. ebi_wen pf4 external bus interface (ebi) write enable output. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 pd15 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 pd14 i2c0 serial data input / output. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pe0 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pe1 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pf6 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pf7 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pf8 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 pb0 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 pb1 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 pb2 timer 1 capture compare input / output channel 2. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 121 alternate location functionality 0 1 2 3 description tim2_cc0 pa8 pa12 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pa13 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pa14 pc10 timer 2 capture compare input / output channel 2. u0_rx pf7 pe1 pa4 pc15 uart0 receive input. u0_tx pf6 pe0 pa3 pc14 uart0 transmit output. also used as receive input in half du- plex communication. us0_clk pe12 pe5 pc9 usart0 clock input / output. us0_cs pe13 pe4 pc8 usart0 chip select input / output. us0_rx pe11 pe6 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pc3 pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 122 5.6.3 gpio pinout overview the specific gpio pins available in EFM32G290 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.18. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb15 pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port f pf9 pf8 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 123 5.7 EFM32G840 (qfn64) 5.7.1 pinout the EFM32G840 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.7. EFM32G840 pinout (top view, not to scale) table 5.19. device pinout qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 0 vss ground. 1 pa0 lcd_seg13 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 lcd_seg14 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 lcd_seg15 tim0_cc2 #0/1 cmu_clk0 #0 4 pa3 lcd_seg16 tim0_cdti0 #0 5 pa4 lcd_seg17 tim0_cdti1 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 124 qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 6 pa5 lcd_seg18 tim0_cdti2 #0 leu1_tx #1 6 pa6 lcd_seg19 leu1_rx #1 8 iovdd_0 digital io power supply 0. 9 pb3 lcd_seg20 pcnt1_s0in #1 us2_tx #1 10 pb4 lcd_seg21 pcnt1_s1in #1 us2_rx #1 11 pb5 lcd_seg22 us2_clk #1 12 pb6 lcd_seg23 us2_cs #1 13 pc4 acmp0_ch4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 14 pc5 acmp0_ch5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 15 pb7 lfxtal_p us1_clk #0 16 pb8 lfxtal_n us1_cs #0 17 pa12 lcd_bcap_ p tim2_cc0 #1 18 pa13 lcd_bcap_ n tim2_cc1 #1 19 pa14 lcd_bext tim2_cc2 #1 20 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 21 pb11 dac0_out0 letim0_out0 #1 22 pb12 dac0_out1 letim0_out1 #1 23 avdd_1 analog power supply 1. 24 pb13 hfxtal_p leu0_tx #1 25 pb14 hfxtal_n leu0_rx #1 26 iovdd_3 digital io power supply 3. 27 avdd_0 analog power supply 0. 28 pd0 adc0_ch0 pcnt2_s0in #0 us1_tx #1 29 pd1 adc0_ch1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 30 pd2 adc0_ch2 tim0_cc1 #3 us1_clk #1 31 pd3 adc0_ch3 tim0_cc2 #3 us1_cs #1 32 pd4 adc0_ch4 leu0_tx #0 33 pd5 adc0_ch5 leu0_rx #0 34 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 35 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 36 pd8 cmu_clk1 #1 37 pc6 acmp0_ch6 leu1_tx #0 i2c0_sda #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 125 qfn64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 38 pc7 acmp0_ch7 leu1_rx #0 i2c0_scl #2 39 vdd_dreg power supply for on-chip voltage regulator. 40 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 41 pe4 lcd_com0 us0_cs #1 42 pe5 lcd_com1 us0_clk #1 43 pe6 lcd_com2 us0_rx #1 44 pe7 lcd_com3 us0_tx #1 45 pc12 acmp1_ch4 cmu_clk0 #1 46 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 47 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 48 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 49 pf0 letim0_out0 #2 dbg_swclk #0/1 50 pf1 letim0_out1 #2 dbg_swdio #0/1 51 pf2 lcd_seg0 acmp1_o #0 dbg_swo #0 52 pf3 lcd_seg1 tim0_cdti0 #2 53 pf4 lcd_seg2 tim0_cdti1 #2 54 pf5 lcd_seg3 tim0_cdti2 #2 55 iovdd_5 digital io power supply 5. 56 pe8 lcd_seg4 pcnt2_s0in #1 57 pe9 lcd_seg5 pcnt2_s1in #1 58 pe10 lcd_seg6 tim1_cc0 #1 us0_tx #0 boot_tx 59 pe11 lcd_seg7 tim1_cc1 #1 us0_rx #0 boot_rx 60 pe12 lcd_seg8 tim1_cc2 #1 us0_clk #0 61 pe13 lcd_seg9 us0_cs #0 acmp0_o #0 62 pe14 lcd_seg10 leu0_tx #2 63 pe15 lcd_seg11 leu0_rx #2 64 pa15 lcd_seg12 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 126 5.7.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.20. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 127 alternate location functionality 0 1 2 3 description dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. lcd_bcap_n pa13 lcd voltage booster (optional), boost capacitor, negative pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bcap_p pa12 lcd voltage booster (optional), boost capacitor, positive pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bext pa14 lcd voltage booster (optional), boost output. if using the lcd voltage booster, connect a 1 uf capacitor between this pin and vss. an external lcd voltage may also be applied to this pin if the booster is not enabled. if avdd is used directly as the lcd supply voltage, this pin may be left unconnected or used as a gpio. lcd_com0 pe4 lcd driver common line number 0. lcd_com1 pe5 lcd driver common line number 1. lcd_com2 pe6 lcd driver common line number 2. lcd_com3 pe7 lcd driver common line number 3. lcd_seg0 pf2 lcd segment line 0. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg1 pf3 lcd segment line 1. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg2 pf4 lcd segment line 2. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg3 pf5 lcd segment line 3. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg4 pe8 lcd segment line 4. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg5 pe9 lcd segment line 5. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg6 pe10 lcd segment line 6. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg7 pe11 lcd segment line 7. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg8 pe12 lcd segment line 8. segments 8, 9, 10 and 11 are controlled by segen2. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 128 alternate location functionality 0 1 2 3 description lcd_seg9 pe13 lcd segment line 9. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg10 pe14 lcd segment line 10. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg11 pe15 lcd segment line 11. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg12 pa15 lcd segment line 12. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg13 pa0 lcd segment line 13. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg14 pa1 lcd segment line 14. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg15 pa2 lcd segment line 15. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg16 pa3 lcd segment line 16. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg17 pa4 lcd segment line 17. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg18 pa5 lcd segment line 18. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg19 pa6 lcd segment line 19. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg20 pb3 lcd segment line 20. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg21 pb4 lcd segment line 21. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg22 pb5 lcd segment line 22. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg23 pb6 lcd segment line 23. segments 20, 21, 22 and 23 are con- trolled by segen5. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pulse counter pcnt0 input number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 129 alternate location functionality 0 1 2 3 description pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. tim2_cc0 pa12 timer 2 capture compare input / output channel 0. tim2_cc1 pa13 timer 2 capture compare input / output channel 1. tim2_cc2 pa14 timer 2 capture compare input / output channel 2. us0_clk pe12 pe5 usart0 clock input / output. us0_cs pe13 pe4 usart0 chip select input / output. us0_rx pe11 pe6 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 130 alternate location functionality 0 1 2 3 description us2_tx pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). 5.7.3 gpio pinout overview the specific gpio pins available in EFM32G840 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.21. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa14 pa13 pa12 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb12 pb11 pb8 pb7 pb6 pb5 pb4 pb3 port c pc15 pc14 pc13 pc12 pc7 pc6 pc5 pc4 port d pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 port f pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 131 5.8 EFM32G842 (tqfp64) 5.8.1 pinout the EFM32G842 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.8. EFM32G842 pinout (top view, not to scale) table 5.22. device pinout tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 1 pa0 lcd_seg13 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 lcd_seg14 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 lcd_seg15 tim0_cc2 #0/1 cmu_clk0 #0 4 pa3 lcd_seg16 tim0_cdti0 #0 5 pa4 lcd_seg17 tim0_cdti1 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 132 tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 6 pa5 lcd_seg18 tim0_cdti2 #0 leu1_tx #1 7 iovdd_0 digital io power supply 0. 8 vss ground. 9 pb3 lcd_seg20 pcnt1_s0in #1 us2_tx #1 10 pb4 lcd_seg21 pcnt1_s1in #1 us2_rx #1 11 pb5 lcd_seg22 us2_clk #1 12 pb6 lcd_seg23 us2_cs #1 13 pc4 acmp0_ch4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 14 pc5 acmp0_ch5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 15 pb7 lfxtal_p us1_clk #0 16 pb8 lfxtal_n us1_cs #0 17 pa12 lcd_bcap_ p tim2_cc0 #1 18 pa13 lcd_bcap_ n tim2_cc1 #1 19 pa14 lcd_bext tim2_cc2 #1 20 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 21 pb11 dac0_out0 letim0_out0 #1 22 vss ground. 23 avdd_1 analog power supply 1. 24 pb13 hfxtal_p leu0_tx #1 25 pb14 hfxtal_n leu0_rx #1 26 iovdd_3 digital io power supply 3. 27 avdd_0 analog power supply 0. 28 pd0 adc0_ch0 pcnt2_s0in #0 us1_tx #1 29 pd1 adc0_ch1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 30 pd2 adc0_ch2 tim0_cc1 #3 us1_clk #1 31 pd3 adc0_ch3 tim0_cc2 #3 us1_cs #1 32 pd4 adc0_ch4 leu0_tx #0 33 pd5 adc0_ch5 leu0_rx #0 34 pd6 adc0_ch6 letim0_out0 #0 i2c0_sda #1 35 pd7 adc0_ch7 letim0_out1 #0 i2c0_scl #1 36 pd8 cmu_clk1 #1 37 pc6 acmp0_ch6 leu1_tx #0 i2c0_sda #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 133 tqfp64 pin# and name pin alternate functionality / description pin # pin name analog timers communication other 38 pc7 acmp0_ch7 leu1_rx #0 i2c0_scl #2 39 vdd_dreg power supply for on-chip voltage regulator. 40 decouple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 41 pe4 lcd_com0 us0_cs #1 42 pe5 lcd_com1 us0_clk #1 43 pe6 lcd_com2 us0_rx #1 44 pe7 lcd_com3 us0_tx #1 45 pc12 acmp1_ch4 cmu_clk0 #1 46 pc13 acmp1_ch5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 47 pc14 acmp1_ch6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 48 pc15 acmp1_ch7 tim0_cdti2 #1/3 tim1_cc2 #0 dbg_swo #1 49 pf0 letim0_out0 #2 dbg_swclk #0/1 50 pf1 letim0_out1 #2 dbg_swdio #0/1 51 pf2 lcd_seg0 acmp1_o #0 dbg_swo #0 52 pf3 lcd_seg1 tim0_cdti0 #2 53 pf4 lcd_seg2 tim0_cdti1 #2 54 pf5 lcd_seg3 tim0_cdti2 #2 55 iovdd_5 digital io power supply 5. 56 vss ground. 57 pe8 lcd_seg4 pcnt2_s0in #1 58 pe9 lcd_seg5 pcnt2_s1in #1 59 pe10 lcd_seg6 tim1_cc0 #1 us0_tx #0 boot_tx 60 pe11 lcd_seg7 tim1_cc1 #1 us0_rx #0 boot_rx 61 pe12 lcd_seg8 tim1_cc2 #1 us0_clk #0 62 pe13 lcd_seg9 us0_cs #0 acmp0_o #0 63 pe14 lcd_seg10 leu0_tx #2 64 pe15 lcd_seg11 leu0_rx #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 134 5.8.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.23. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 analog comparator acmp0, digital output. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 135 alternate location functionality 0 1 2 3 description dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. lcd_bcap_n pa13 lcd voltage booster (optional), boost capacitor, negative pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bcap_p pa12 lcd voltage booster (optional), boost capacitor, positive pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bext pa14 lcd voltage booster (optional), boost output. if using the lcd voltage booster, connect a 1 uf capacitor between this pin and vss. an external lcd voltage may also be applied to this pin if the booster is not enabled. if avdd is used directly as the lcd supply voltage, this pin may be left unconnected or used as a gpio. lcd_com0 pe4 lcd driver common line number 0. lcd_com1 pe5 lcd driver common line number 1. lcd_com2 pe6 lcd driver common line number 2. lcd_com3 pe7 lcd driver common line number 3. lcd_seg0 pf2 lcd segment line 0. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg1 pf3 lcd segment line 1. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg2 pf4 lcd segment line 2. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg3 pf5 lcd segment line 3. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg4 pe8 lcd segment line 4. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg5 pe9 lcd segment line 5. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg6 pe10 lcd segment line 6. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg7 pe11 lcd segment line 7. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg8 pe12 lcd segment line 8. segments 8, 9, 10 and 11 are controlled by segen2. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 136 alternate location functionality 0 1 2 3 description lcd_seg9 pe13 lcd segment line 9. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg10 pe14 lcd segment line 10. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg11 pe15 lcd segment line 11. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg13 pa0 lcd segment line 13. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg14 pa1 lcd segment line 14. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg15 pa2 lcd segment line 15. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg16 pa3 lcd segment line 16. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg17 pa4 lcd segment line 17. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg18 pa5 lcd segment line 18. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg20 pb3 lcd segment line 20. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg21 pb4 lcd segment line 21. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg22 pb5 lcd segment line 22. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg23 pb6 lcd segment line 23. segments 20, 21, 22 and 23 are con- trolled by segen5. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 137 alternate location functionality 0 1 2 3 description tim0_cc0 pa0 pa0 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 timer 1 capture compare input / output channel 2. tim2_cc0 pa12 timer 2 capture compare input / output channel 0. tim2_cc1 pa13 timer 2 capture compare input / output channel 1. tim2_cc2 pa14 timer 2 capture compare input / output channel 2. us0_clk pe12 pe5 usart0 clock input / output. us0_cs pe13 pe4 usart0 chip select input / output. us0_rx pe11 pe6 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 138 5.8.3 gpio pinout overview the specific gpio pins available in EFM32G842 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.24. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa14 pa13 pa12 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb11 pb8 pb7 pb6 pb5 pb4 pb3 port c pc15 pc14 pc13 pc12 pc7 pc6 pc5 pc4 port d pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 port f pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 139 5.9 EFM32G880 (lqfp100) 5.9.1 pinout the EFM32G880 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.9. EFM32G880 pinout (top view, not to scale) table 5.25. device pinout lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 1 pa0 lcd_seg 13 ebi_ad09 #0 tim0_cc0 #0/1 i2c0_sda #0 2 pa1 lcd_seg 14 ebi_ad10 #0 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 3 pa2 lcd_seg 15 ebi_ad11 #0 tim0_cc2 #0/1 cmu_clk0 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 140 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 4 pa3 lcd_seg 16 ebi_ad12 #0 tim0_cdti0 #0 u0_tx #2 5 pa4 lcd_seg 17 ebi_ad13 #0 tim0_cdti1 #0 u0_rx #2 6 pa5 lcd_seg 18 ebi_ad14 #0 tim0_cdti2 #0 leu1_tx #1 7 pa6 lcd_seg 19 ebi_ad15 #0 leu1_rx #1 8 iovdd_0 digital io power supply 0. 9 pb0 lcd_seg 32 tim1_cc0 #2 10 pb1 lcd_seg 33 tim1_cc1 #2 11 pb2 lcd_seg 34 tim1_cc2 #2 12 pb3 lcd_seg 20 pcnt1_s0in #1 us2_tx #1 13 pb4 lcd_seg 21 pcnt1_s1in #1 us2_rx #1 14 pb5 lcd_seg 22 us2_clk #1 15 pb6 lcd_seg 23 us2_cs #1 16 vss ground. 17 iovdd_1 digital io power supply 1. 18 pc0 acmp0_c h0 pcnt0_s0in #2 us1_tx #0 19 pc1 acmp0_c h1 pcnt0_s1in #2 us1_rx #0 20 pc2 acmp0_c h2 us2_tx #0 21 pc3 acmp0_c h3 us2_rx #0 22 pc4 acmp0_c h4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 23 pc5 acmp0_c h5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 24 pb7 lfxtal_p us1_clk #0 25 pb8 lfxtal_n us1_cs #0 26 pa7 lcd_seg 35 27 pa8 lcd_seg 36 tim2_cc0 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 141 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 28 pa9 lcd_seg 37 tim2_cc1 #0 29 pa10 lcd_seg 38 tim2_cc2 #0 30 pa11 lcd_seg 39 31 iovdd_2 digital io power supply 2. 32 vss ground. 33 pa12 lcd_bca p_p tim2_cc0 #1 34 pa13 lcd_bca p_n tim2_cc1 #1 35 pa14 lcd_bex t tim2_cc2 #1 36 resetn reset input, active low.to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 37 pb9 38 pb10 39 pb11 dac0_ou t0 letim0_out0 #1 40 pb12 dac0_ou t1 letim0_out1 #1 41 avdd_1 analog power supply 1. 42 pb13 hfxtal_ p leu0_tx #1 43 pb14 hfxtal_ n leu0_rx #1 44 iovdd_3 digital io power supply 3. 45 avdd_0 analog power supply 0. 46 pd0 adc0_ch 0 pcnt2_s0in #0 us1_tx #1 47 pd1 adc0_ch 1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 48 pd2 adc0_ch 2 tim0_cc1 #3 us1_clk #1 49 pd3 adc0_ch 3 tim0_cc2 #3 us1_cs #1 50 pd4 adc0_ch 4 leu0_tx #0 51 pd5 adc0_ch 5 leu0_rx #0 52 pd6 adc0_ch 6 letim0_out0 #0 i2c0_sda #1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 142 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 53 pd7 adc0_ch 7 letim0_out1 #0 i2c0_scl #1 54 pd8 cmu_clk1 #1 55 pc6 acmp0_c h6 leu1_tx #0 i2c0_sda #2 56 pc7 acmp0_c h7 leu1_rx #0 i2c0_scl #2 57 vdd_dre g power supply for on-chip voltage regulator. 58 vss ground. 59 decou- ple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. 60 pe0 pcnt0_s0in #1 u0_tx #1 61 pe1 pcnt0_s1in #1 u0_rx #1 62 pe2 acmp0_o #1 63 pe3 acmp1_o #1 64 pe4 lcd_com 0 us0_cs #1 65 pe5 lcd_com 1 us0_clk #1 66 pe6 lcd_com 2 us0_rx #1 67 pe7 lcd_com 3 us0_tx #1 68 pc8 acmp1_c h0 tim2_cc0 #2 us0_cs #2 69 pc9 acmp1_c h1 tim2_cc1 #2 us0_clk #2 70 pc10 acmp1_c h2 tim2_cc2 #2 us0_rx #2 71 pc11 acmp1_c h3 us0_tx #2 72 pc12 acmp1_c h4 cmu_clk0 #1 73 pc13 acmp1_c h5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 74 pc14 acmp1_c h6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 u0_tx #3 75 pc15 acmp1_c h7 tim0_cdti2 #1/3 tim1_cc2 #0 u0_rx #3 dbg_swo #1 76 pf0 letim0_out0 #2 dbg_swclk #0/1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 143 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 77 pf1 letim0_out1 #2 dbg_swdio #0/1 78 pf2 lcd_seg 0 ebi_ardy #0 acmp1_o #0 dbg_swo #0 79 pf3 lcd_seg 1 ebi_ale #0 tim0_cdti0 #2 80 pf4 lcd_seg 2 ebi_wen #0 tim0_cdti1 #2 81 pf5 lcd_seg 3 ebi_ren #0 tim0_cdti2 #2 82 iovdd_5 digital io power supply 5. 83 vss ground. 84 pf6 lcd_seg 24 tim0_cc0 #2 u0_tx #0 85 pf7 lcd_seg 25 tim0_cc1 #2 u0_rx #0 86 pf8 lcd_seg 26 tim0_cc2 #2 87 pf9 lcd_seg 27 88 pd9 lcd_seg 28 ebi_cs0 #0 89 pd10 lcd_seg 29 ebi_cs1 #0 90 pd11 lcd_seg 30 ebi_cs2 #0 91 pd12 lcd_seg 31 ebi_cs3 #0 92 pe8 lcd_seg 4 ebi_ad00 #0 pcnt2_s0in #1 93 pe9 lcd_seg 5 ebi_ad01 #0 pcnt2_s1in #1 94 pe10 lcd_seg 6 ebi_ad02 #0 tim1_cc0 #1 us0_tx #0 boot_tx 95 pe11 lcd_seg 7 ebi_ad03 #0 tim1_cc1 #1 us0_rx #0 boot_rx 96 pe12 lcd_seg 8 ebi_ad04 #0 tim1_cc2 #1 us0_clk #0 97 pe13 lcd_seg 9 ebi_ad05 #0 us0_cs #0 acmp0_o #0 98 pe14 lcd_seg 10 ebi_ad06 #0 leu0_tx #2 99 pe15 lcd_seg 11 ebi_ad07 #0 leu0_rx #2 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 144 lqfp100 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other 100 pa15 lcd_seg 12 ebi_ad08 #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 145 5.9.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.26. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 pe2 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 pe3 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 146 alternate location functionality 0 1 2 3 description dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. ebi_ad00 pe8 external bus interface (ebi) address and data input / output pin 00. ebi_ad01 pe9 external bus interface (ebi) address and data input / output pin 01. ebi_ad02 pe10 external bus interface (ebi) address and data input / output pin 02. ebi_ad03 pe11 external bus interface (ebi) address and data input / output pin 03. ebi_ad04 pe12 external bus interface (ebi) address and data input / output pin 04. ebi_ad05 pe13 external bus interface (ebi) address and data input / output pin 05. ebi_ad06 pe14 external bus interface (ebi) address and data input / output pin 06. ebi_ad07 pe15 external bus interface (ebi) address and data input / output pin 07. ebi_ad08 pa15 external bus interface (ebi) address and data input / output pin 08. ebi_ad09 pa0 external bus interface (ebi) address and data input / output pin 09. ebi_ad10 pa1 external bus interface (ebi) address and data input / output pin 10. ebi_ad11 pa2 external bus interface (ebi) address and data input / output pin 11. ebi_ad12 pa3 external bus interface (ebi) address and data input / output pin 12. ebi_ad13 pa4 external bus interface (ebi) address and data input / output pin 13. ebi_ad14 pa5 external bus interface (ebi) address and data input / output pin 14. ebi_ad15 pa6 external bus interface (ebi) address and data input / output pin 15. ebi_ale pf3 external bus interface (ebi) address latch enable output. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 147 alternate location functionality 0 1 2 3 description ebi_ardy pf2 external bus interface (ebi) hardware ready control input. ebi_cs0 pd9 external bus interface (ebi) chip select output 0. ebi_cs1 pd10 external bus interface (ebi) chip select output 1. ebi_cs2 pd11 external bus interface (ebi) chip select output 2. ebi_cs3 pd12 external bus interface (ebi) chip select output 3. ebi_ren pf5 external bus interface (ebi) read enable output. ebi_wen pf4 external bus interface (ebi) write enable output. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 i2c0 serial data input / output. lcd_bcap_n pa13 lcd voltage booster (optional), boost capacitor, negative pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bcap_p pa12 lcd voltage booster (optional), boost capacitor, positive pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bext pa14 lcd voltage booster (optional), boost output. if using the lcd voltage booster, connect a 1 uf capacitor between this pin and vss. an external lcd voltage may also be applied to this pin if the booster is not enabled. if avdd is used directly as the lcd supply voltage, this pin may be left unconnected or used as a gpio. lcd_com0 pe4 lcd driver common line number 0. lcd_com1 pe5 lcd driver common line number 1. lcd_com2 pe6 lcd driver common line number 2. lcd_com3 pe7 lcd driver common line number 3. lcd_seg0 pf2 lcd segment line 0. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg1 pf3 lcd segment line 1. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg2 pf4 lcd segment line 2. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg3 pf5 lcd segment line 3. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg4 pe8 lcd segment line 4. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg5 pe9 lcd segment line 5. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg6 pe10 lcd segment line 6. segments 4, 5, 6 and 7 are controlled by segen1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 148 alternate location functionality 0 1 2 3 description lcd_seg7 pe11 lcd segment line 7. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg8 pe12 lcd segment line 8. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg9 pe13 lcd segment line 9. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg10 pe14 lcd segment line 10. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg11 pe15 lcd segment line 11. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg12 pa15 lcd segment line 12. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg13 pa0 lcd segment line 13. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg14 pa1 lcd segment line 14. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg15 pa2 lcd segment line 15. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg16 pa3 lcd segment line 16. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg17 pa4 lcd segment line 17. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg18 pa5 lcd segment line 18. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg19 pa6 lcd segment line 19. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg20 pb3 lcd segment line 20. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg21 pb4 lcd segment line 21. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg22 pb5 lcd segment line 22. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg23 pb6 lcd segment line 23. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg24 pf6 lcd segment line 24. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg25 pf7 lcd segment line 25. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg26 pf8 lcd segment line 26. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg27 pf9 lcd segment line 27. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg28 pd9 lcd segment line 28. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg29 pd10 lcd segment line 29. segments 28, 29, 30 and 31 are con- trolled by segen7. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 149 alternate location functionality 0 1 2 3 description lcd_seg30 pd11 lcd segment line 30. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg31 pd12 lcd segment line 31. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg32 pb0 lcd segment line 32. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg33 pb1 lcd segment line 33. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg34 pb2 lcd segment line 34. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg35 pa7 lcd segment line 35. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg36 pa8 lcd segment line 36. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg37 pa9 lcd segment line 37. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg38 pa10 lcd segment line 38. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg39 pa11 lcd segment line 39. segments 36, 37, 38 and 39 are con- trolled by segen9. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pe0 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pe1 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pf6 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pf7 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pf8 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 150 alternate location functionality 0 1 2 3 description tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 pb0 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 pb1 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 pb2 timer 1 capture compare input / output channel 2. tim2_cc0 pa8 pa12 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pa13 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pa14 pc10 timer 2 capture compare input / output channel 2. u0_rx pf7 pe1 pa4 pc15 uart0 receive input. u0_tx pf6 pe0 pa3 pc14 uart0 transmit output. also used as receive input in half du- plex communication. us0_clk pe12 pe5 pc9 usart0 clock input / output. us0_cs pe13 pe4 pc8 usart0 chip select input / output. us0_rx pe11 pe6 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pc3 pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 151 5.9.3 gpio pinout overview the specific gpio pins available in EFM32G880 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.27. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port f pf9 pf8 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 152 5.10 EFM32G890 (bga112) 5.10.1 pinout the EFM32G890 pinout is shown in the following figure and table. alternate locations are denoted by "#" followed by the location num- ber (multiple locations on the same pin are split with "/"). alternate locations can be configured in the location bitfield in the *_route register in the module in question. figure 5.10. EFM32G890 pinout (top view, not to scale) table 5.28. device pinout bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other a1 pe15 lcd_seg 11 ebi_ad07 #0 leu0_rx #2 a2 pe14 lcd_seg 10 ebi_ad06 #0 leu0_tx #2 a3 pe12 lcd_seg 8 ebi_ad04 #0 tim1_cc2 #1 us0_clk #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 153 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other a4 pe9 lcd_seg 5 ebi_ad01 #0 pcnt2_s1in #1 a5 pd10 lcd_seg 29 ebi_cs1 #0 a6 pf7 lcd_seg 25 tim0_cc1 #2 u0_rx #0 a7 pf5 lcd_seg 3 ebi_ren #0 tim0_cdti2 #2 a8 pf4 lcd_seg 2 ebi_wen #0 tim0_cdti1 #2 a9 pe4 lcd_com 0 us0_cs #1 a10 pc14 acmp1_c h6 tim0_cdti1 #1/3 tim1_cc1 #0 pcnt0_s1in #0 u0_tx #3 a11 pc15 acmp1_c h7 tim0_cdti2 #1/3 tim1_cc2 #0 u0_rx #3 dbg_swo #1 b1 pa15 lcd_seg 12 ebi_ad08 #0 b2 pe13 lcd_seg 9 ebi_ad05 #0 us0_cs #0 acmp0_o #0 b3 pe11 lcd_seg 7 ebi_ad03 #0 tim1_cc1 #1 us0_rx #0 boot_rx b4 pe8 lcd_seg 4 ebi_ad00 #0 pcnt2_s0in #1 b5 pd11 lcd_seg 30 ebi_cs2 #0 b6 pf8 lcd_seg 26 tim0_cc2 #2 b7 pf6 lcd_seg 24 tim0_cc0 #2 u0_tx #0 b8 pf3 lcd_seg 1 ebi_ale #0 tim0_cdti0 #2 b9 pe5 lcd_com 1 us0_clk #1 b10 pc12 acmp1_c h4 cmu_clk0 #1 b11 pc13 acmp1_c h5 tim0_cdti0 #1/3 tim1_cc0 #0 pcnt0_s0in #0 c1 pa1 lcd_seg 14 ebi_ad10 #0 tim0_cc1 #0/1 i2c0_scl #0 cmu_clk1 #0 c2 pa0 lcd_seg 13 ebi_ad09 #0 tim0_cc0 #0/1 i2c0_sda #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 154 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other c3 pe10 lcd_seg 6 ebi_ad02 #0 tim1_cc0 #1 us0_tx #0 boot_tx c4 pd13 c5 pd12 lcd_seg 31 ebi_cs3 #0 c6 pf9 lcd_seg 27 c7 vss ground. c8 pf2 lcd_seg 0 ebi_ardy #0 acmp1_o #0 dbg_swo #0 c9 pe6 lcd_com 2 us0_rx #1 c10 pc10 acmp1_c h2 tim2_cc2 #2 us0_rx #2 c11 pc11 acmp1_c h3 us0_tx #2 d1 pa3 lcd_seg 16 ebi_ad12 #0 tim0_cdti0 #0 u0_tx #2 d2 pa2 lcd_seg 15 ebi_ad11 #0 tim0_cc2 #0/1 cmu_clk0 #0 d3 pb15 d4 vss ground. d5 iovdd_6 digital io power supply 6. d6 pd9 lcd_seg 28 ebi_cs0 #0 d7 iovdd_5 digital io power supply 5. d8 pf1 letim0_out1 #2 dbg_swdio #0/1 d9 pe7 lcd_com 3 us0_tx #1 d10 pc8 acmp1_c h0 tim2_cc0 #2 us0_cs #2 d11 pc9 acmp1_c h1 tim2_cc1 #2 us0_clk #2 e1 pa6 lcd_seg 19 ebi_ad15 #0 leu1_rx #1 e2 pa5 lcd_seg 18 ebi_ad14 #0 tim0_cdti2 #0 leu1_tx #1 e3 pa4 lcd_seg 17 ebi_ad13 #0 tim0_cdti1 #0 u0_rx #2 e4 pb0 lcd_seg 32 tim1_cc0 #2 e8 pf0 letim0_out0 #2 dbg_swclk #0/1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 155 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other e9 pe0 pcnt0_s0in #1 u0_tx #1 e10 pe1 pcnt0_s1in #1 u0_rx #1 e11 pe3 acmp1_o #1 f1 pb1 lcd_seg 33 tim1_cc1 #2 f2 pb2 lcd_seg 34 tim1_cc2 #2 f3 pb3 lcd_seg 20 pcnt1_s0in #1 us2_tx #1 f4 pb4 lcd_seg 21 pcnt1_s1in #1 us2_rx #1 f8 vdd_dre g power supply for on-chip voltage regulator. f9 vss_dre g ground for on-chip voltage regulator. f10 pe2 acmp0_o #1 f11 decou- ple decouple output for on-chip voltage regulator. an external capacitance of size c decouple is required at this pin. g1 pb5 lcd_seg 22 us2_clk #1 g2 pb6 lcd_seg 23 us2_cs #1 g3 vss ground. g4 iovdd_0 digital io power supply 0. g8 iovdd_4 digital io power supply 4. g9 vss ground. g10 pc6 acmp0_c h6 leu1_tx #0 i2c0_sda #2 g11 pc7 acmp0_c h7 leu1_rx #0 i2c0_scl #2 h1 pc0 acmp0_c h0 pcnt0_s0in #2 us1_tx #0 h2 pc2 acmp0_c h2 us2_tx #0 h3 pd14 i2c0_sda #3 h4 pa7 lcd_seg 35 h5 pa8 lcd_seg 36 tim2_cc0 #0 h6 vss ground. h7 iovdd_3 digital io power supply 3. h8 pd8 cmu_clk1 #1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 156 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other h9 pd5 adc0_ch 5 leu0_rx #0 h10 pd6 adc0_ch 6 letim0_out0 #0 i2c0_sda #1 h11 pd7 adc0_ch 7 letim0_out1 #0 i2c0_scl #1 j1 pc1 acmp0_c h1 pcnt0_s1in #2 us1_rx #0 j2 pc3 acmp0_c h3 us2_rx #0 j3 pd15 i2c0_scl #3 j4 pa12 lcd_bca p_p tim2_cc0 #1 j5 pa9 lcd_seg 37 tim2_cc1 #0 j6 pa10 lcd_seg 38 tim2_cc2 #0 j7 pb9 j8 pb10 j9 pd2 adc0_ch 2 tim0_cc1 #3 us1_clk #1 j10 pd3 adc0_ch 3 tim0_cc2 #3 us1_cs #1 j11 pd4 adc0_ch 4 leu0_tx #0 k1 pb7 lfxtal_p us1_clk #0 k2 pc4 acmp0_c h4 letim0_out0 #3 pcnt1_s0in #0 us2_clk #0 k3 pa13 lcd_bca p_n tim2_cc1 #1 k4 vss ground. k5 pa11 lcd_seg 39 k6 resetn reset input, active low. to apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. k7 avss_1 analog ground 1. k8 avdd_2 analog power supply 2. k9 avdd_1 analog power supply 1. k10 avss_0 analog ground 0. k11 pd1 adc0_ch 1 tim0_cc0 #3 pcnt2_s1in #0 us1_rx #1 l1 pb8 lfxtal_n us1_cs #0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 157 bga112 pin# and name pin alternate functionality / description pin # pin name analog ebi timers communication other l2 pc5 acmp0_c h5 letim0_out1 #3 pcnt1_s1in #0 us2_cs #0 l3 pa14 lcd_bex t tim2_cc2 #1 l4 iovdd_1 digital io power supply 1. l5 pb11 dac0_ou t0 letim0_out0 #1 l6 pb12 dac0_ou t1 letim0_out1 #1 l7 avss_2 analog ground 2. l8 pb13 hfxtal_ p leu0_tx #1 l9 pb14 hfxtal_ n leu0_rx #1 l10 avdd_0 analog power supply 0. l11 pd0 adc0_ch 0 pcnt2_s0in #0 us1_tx #1 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 158 5.10.2 alternate functionality pinout a wide selection of alternate functionality is available for multiplexing to various pins. this is shown in the following table. the table shows the name of the alternate functionality in the first column, followed by columns showing the possible location bitfield settings. note: some functionality, such as analog interfaces, do not have alternate settings or a location bitfield. in these cases, the pinout is shown in the column corresponding to location 0. table 5.29. alternate functionality overview alternate location functionality 0 1 2 3 description acmp0_ch0 pc0 analog comparator acmp0, channel 0. acmp0_ch1 pc1 analog comparator acmp0, channel 1. acmp0_ch2 pc2 analog comparator acmp0, channel 2. acmp0_ch3 pc3 analog comparator acmp0, channel 3. acmp0_ch4 pc4 analog comparator acmp0, channel 4. acmp0_ch5 pc5 analog comparator acmp0, channel 5. acmp0_ch6 pc6 analog comparator acmp0, channel 6. acmp0_ch7 pc7 analog comparator acmp0, channel 7. acmp0_o pe13 pe2 analog comparator acmp0, digital output. acmp1_ch0 pc8 analog comparator acmp1, channel 0. acmp1_ch1 pc9 analog comparator acmp1, channel 1. acmp1_ch2 pc10 analog comparator acmp1, channel 2. acmp1_ch3 pc11 analog comparator acmp1, channel 3. acmp1_ch4 pc12 analog comparator acmp1, channel 4. acmp1_ch5 pc13 analog comparator acmp1, channel 5. acmp1_ch6 pc14 analog comparator acmp1, channel 6. acmp1_ch7 pc15 analog comparator acmp1, channel 7. acmp1_o pf2 pe3 analog comparator acmp1, digital output. adc0_ch0 pd0 analog to digital converter adc0, input channel number 0. adc0_ch1 pd1 analog to digital converter adc0, input channel number 1. adc0_ch2 pd2 analog to digital converter adc0, input channel number 2. adc0_ch3 pd3 analog to digital converter adc0, input channel number 3. adc0_ch4 pd4 analog to digital converter adc0, input channel number 4. adc0_ch5 pd5 analog to digital converter adc0, input channel number 5. adc0_ch6 pd6 analog to digital converter adc0, input channel number 6. adc0_ch7 pd7 analog to digital converter adc0, input channel number 7. boot_rx pe11 bootloader rx. boot_tx pe10 bootloader tx. cmu_clk0 pa2 pc12 clock management unit, clock output number 0. cmu_clk1 pa1 pd8 clock management unit, clock output number 1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 159 alternate location functionality 0 1 2 3 description dac0_out0 pb11 digital to analog converter dac0 output channel number 0. dac0_out1 pb12 digital to analog converter dac0 output channel number 1. dbg_swclk pf0 pf0 debug-interface serial wire clock input. note that this function is enabled to pin out of reset, and has a built-in pull down. dbg_swdio pf1 pf1 debug-interface serial wire data input / output. note that this function is enabled to pin out of reset, and has a built-in pull up. dbg_swo pf2 pc15 debug-interface serial wire viewer output. note that this function is not enabled after reset, and must be enabled by software to be used. ebi_ad00 pe8 external bus interface (ebi) address and data input / output pin 00. ebi_ad01 pe9 external bus interface (ebi) address and data input / output pin 01. ebi_ad02 pe10 external bus interface (ebi) address and data input / output pin 02. ebi_ad03 pe11 external bus interface (ebi) address and data input / output pin 03. ebi_ad04 pe12 external bus interface (ebi) address and data input / output pin 04. ebi_ad05 pe13 external bus interface (ebi) address and data input / output pin 05. ebi_ad06 pe14 external bus interface (ebi) address and data input / output pin 06. ebi_ad07 pe15 external bus interface (ebi) address and data input / output pin 07. ebi_ad08 pa15 external bus interface (ebi) address and data input / output pin 08. ebi_ad09 pa0 external bus interface (ebi) address and data input / output pin 09. ebi_ad10 pa1 external bus interface (ebi) address and data input / output pin 10. ebi_ad11 pa2 external bus interface (ebi) address and data input / output pin 11. ebi_ad12 pa3 external bus interface (ebi) address and data input / output pin 12. ebi_ad13 pa4 external bus interface (ebi) address and data input / output pin 13. ebi_ad14 pa5 external bus interface (ebi) address and data input / output pin 14. ebi_ad15 pa6 external bus interface (ebi) address and data input / output pin 15. ebi_ale pf3 external bus interface (ebi) address latch enable output. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 160 alternate location functionality 0 1 2 3 description ebi_ardy pf2 external bus interface (ebi) hardware ready control input. ebi_cs0 pd9 external bus interface (ebi) chip select output 0. ebi_cs1 pd10 external bus interface (ebi) chip select output 1. ebi_cs2 pd11 external bus interface (ebi) chip select output 2. ebi_cs3 pd12 external bus interface (ebi) chip select output 3. ebi_ren pf5 external bus interface (ebi) read enable output. ebi_wen pf4 external bus interface (ebi) write enable output. hfxtal_n pb14 high frequency crystal negative pin. also used as external optional clock input pin. hfxtal_p pb13 high frequency crystal positive pin. i2c0_scl pa1 pd7 pc7 pd15 i2c0 serial clock line input / output. i2c0_sda pa0 pd6 pc6 pd14 i2c0 serial data input / output. lcd_bcap_n pa13 lcd voltage booster (optional), boost capacitor, negative pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bcap_p pa12 lcd voltage booster (optional), boost capacitor, positive pin. if using the lcd voltage booster, connect a 22 nf capacitor between lcd_bcap_n and lcd_bcap_p. lcd_bext pa14 lcd voltage booster (optional), boost output. if using the lcd voltage booster, connect a 1 uf capacitor between this pin and vss. an external lcd voltage may also be applied to this pin if the booster is not enabled. if avdd is used directly as the lcd supply voltage, this pin may be left unconnected or used as a gpio. lcd_com0 pe4 lcd driver common line number 0. lcd_com1 pe5 lcd driver common line number 1. lcd_com2 pe6 lcd driver common line number 2. lcd_com3 pe7 lcd driver common line number 3. lcd_seg0 pf2 lcd segment line 0. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg1 pf3 lcd segment line 1. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg2 pf4 lcd segment line 2. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg3 pf5 lcd segment line 3. segments 0, 1, 2 and 3 are controlled by segen0. lcd_seg4 pe8 lcd segment line 4. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg5 pe9 lcd segment line 5. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg6 pe10 lcd segment line 6. segments 4, 5, 6 and 7 are controlled by segen1. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 161 alternate location functionality 0 1 2 3 description lcd_seg7 pe11 lcd segment line 7. segments 4, 5, 6 and 7 are controlled by segen1. lcd_seg8 pe12 lcd segment line 8. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg9 pe13 lcd segment line 9. segments 8, 9, 10 and 11 are controlled by segen2. lcd_seg10 pe14 lcd segment line 10. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg11 pe15 lcd segment line 11. segments 8, 9, 10 and 11 are control- led by segen2. lcd_seg12 pa15 lcd segment line 12. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg13 pa0 lcd segment line 13. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg14 pa1 lcd segment line 14. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg15 pa2 lcd segment line 15. segments 12, 13, 14 and 15 are con- trolled by segen3. lcd_seg16 pa3 lcd segment line 16. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg17 pa4 lcd segment line 17. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg18 pa5 lcd segment line 18. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg19 pa6 lcd segment line 19. segments 16, 17, 18 and 19 are con- trolled by segen4. lcd_seg20 pb3 lcd segment line 20. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg21 pb4 lcd segment line 21. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg22 pb5 lcd segment line 22. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg23 pb6 lcd segment line 23. segments 20, 21, 22 and 23 are con- trolled by segen5. lcd_seg24 pf6 lcd segment line 24. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg25 pf7 lcd segment line 25. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg26 pf8 lcd segment line 26. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg27 pf9 lcd segment line 27. segments 24, 25, 26 and 27 are con- trolled by segen6. lcd_seg28 pd9 lcd segment line 28. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg29 pd10 lcd segment line 29. segments 28, 29, 30 and 31 are con- trolled by segen7. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 162 alternate location functionality 0 1 2 3 description lcd_seg30 pd11 lcd segment line 30. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg31 pd12 lcd segment line 31. segments 28, 29, 30 and 31 are con- trolled by segen7. lcd_seg32 pb0 lcd segment line 32. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg33 pb1 lcd segment line 33. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg34 pb2 lcd segment line 34. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg35 pa7 lcd segment line 35. segments 32, 33, 34 and 35 are con- trolled by segen8. lcd_seg36 pa8 lcd segment line 36. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg37 pa9 lcd segment line 37. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg38 pa10 lcd segment line 38. segments 36, 37, 38 and 39 are con- trolled by segen9. lcd_seg39 pa11 lcd segment line 39. segments 36, 37, 38 and 39 are con- trolled by segen9. letim0_out0 pd6 pb11 pf0 pc4 low energy timer letim0, output channel 0. letim0_out1 pd7 pb12 pf1 pc5 low energy timer letim0, output channel 1. leu0_rx pd5 pb14 pe15 leuart0 receive input. leu0_tx pd4 pb13 pe14 leuart0 transmit output. also used as receive input in half duplex communication. leu1_rx pc7 pa6 leuart1 receive input. leu1_tx pc6 pa5 leuart1 transmit output. also used as receive input in half duplex communication. lfxtal_n pb8 low frequency crystal (typically 32.768 khz) negative pin. al- so used as an optional external clock input pin. lfxtal_p pb7 low frequency crystal (typically 32.768 khz) positive pin. pcnt0_s0in pc13 pe0 pc0 pulse counter pcnt0 input number 0. pcnt0_s1in pc14 pe1 pc1 pulse counter pcnt0 input number 1. pcnt1_s0in pc4 pb3 pulse counter pcnt1 input number 0. pcnt1_s1in pc5 pb4 pulse counter pcnt1 input number 1. pcnt2_s0in pd0 pe8 pulse counter pcnt2 input number 0. pcnt2_s1in pd1 pe9 pulse counter pcnt2 input number 1. tim0_cc0 pa0 pa0 pf6 pd1 timer 0 capture compare input / output channel 0. tim0_cc1 pa1 pa1 pf7 pd2 timer 0 capture compare input / output channel 1. tim0_cc2 pa2 pa2 pf8 pd3 timer 0 capture compare input / output channel 2. tim0_cdti0 pa3 pc13 pf3 pc13 timer 0 complimentary deat time insertion channel 0. EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 163 alternate location functionality 0 1 2 3 description tim0_cdti1 pa4 pc14 pf4 pc14 timer 0 complimentary deat time insertion channel 1. tim0_cdti2 pa5 pc15 pf5 pc15 timer 0 complimentary deat time insertion channel 2. tim1_cc0 pc13 pe10 pb0 timer 1 capture compare input / output channel 0. tim1_cc1 pc14 pe11 pb1 timer 1 capture compare input / output channel 1. tim1_cc2 pc15 pe12 pb2 timer 1 capture compare input / output channel 2. tim2_cc0 pa8 pa12 pc8 timer 2 capture compare input / output channel 0. tim2_cc1 pa9 pa13 pc9 timer 2 capture compare input / output channel 1. tim2_cc2 pa10 pa14 pc10 timer 2 capture compare input / output channel 2. u0_rx pf7 pe1 pa4 pc15 uart0 receive input. u0_tx pf6 pe0 pa3 pc14 uart0 transmit output. also used as receive input in half du- plex communication. us0_clk pe12 pe5 pc9 usart0 clock input / output. us0_cs pe13 pe4 pc8 usart0 chip select input / output. us0_rx pe11 pe6 pc10 usart0 asynchronous receive. usart0 synchronous mode master input / slave output (mi- so). us0_tx pe10 pe7 pc11 usart0 asynchronous transmit.also used as receive input in half duplex communication. usart0 synchronous mode master output / slave input (mosi). us1_clk pb7 pd2 usart1 clock input / output. us1_cs pb8 pd3 usart1 chip select input / output. us1_rx pc1 pd1 usart1 asynchronous receive. usart1 synchronous mode master input / slave output (mi- so). us1_tx pc0 pd0 usart1 asynchronous transmit.also used as receive input in half duplex communication. usart1 synchronous mode master output / slave input (mosi). us2_clk pc4 pb5 usart2 clock input / output. us2_cs pc5 pb6 usart2 chip select input / output. us2_rx pc3 pb4 usart2 asynchronous receive. usart2 synchronous mode master input / slave output (mi- so). us2_tx pc2 pb3 usart2 asynchronous transmit.also used as receive input in half duplex communication. usart2 synchronous mode master output / slave input (mosi). EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 164 5.10.3 gpio pinout overview the specific gpio pins available in EFM32G890 is shown in the following table. each gpio port is organized as 16-bit ports indicated by letters a through f, and the individual pin on this port is indicated by a number from 15 down to 0. table 5.30. gpio pinout port pin 15 pin 14 pin 13 pin 12 pin 11 pin 10 pin 9 pin 8 pin 7 pin 6 pin 5 pin 4 pin 3 pin 2 pin 1 pin 0 port a pa15 pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 port b pb15 pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port c pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port d pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 port e pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port f pf9 pf8 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 EFM32G data sheet pin definitions silabs.com | building a more connected world. rev. 2.10 | 165 6. bga112 package specifications 6.1 bga112 package dimensions top view bottom view side view rev: 97spp01315a_x03_06jun11 figure 6.1. bga112 note: 1. the dimensions in parenthesis are reference. 2. datum 'c' and seating plane are defined by the crown of the solder balls. 3. all dimensions are in millimeters. the bga112 package uses sac105 solderballs. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx . EFM32G data sheet bga112 package specifications silabs.com | building a more connected world. rev. 2.10 | 166 6.2 bga112 pcb layout a b d e figure 6.2. bga112 pcb land pattern table 6.1. bga112 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) a 0.35 b 0.80 d 8.00 e 8.00 a b d e figure 6.3. bga112 pcb solder mask table 6.2. bga112 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) a 0.48 b 0.80 d 8.00 e 8.00 EFM32G data sheet bga112 package specifications silabs.com | building a more connected world. rev. 2.10 | 167 a b d e figure 6.4. bga112 pcb stencil design table 6.3. bga112 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) a 0.33 b 0.80 d 8.00 e 8.00 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see pin definitions. EFM32G data sheet bga112 package specifications silabs.com | building a more connected world. rev. 2.10 | 168 6.3 bga112 package marking in the illustration below package fields and position are shown. figure 6.5. example chip marking (top view) EFM32G data sheet bga112 package specifications silabs.com | building a more connected world. rev. 2.10 | 169 7. lqfp100 package specifications 7.1 lqfp100 package dimensions rev: 98a0100qp043_03may2007 figure 7.1. lqfp100 note: 1. datum 't', 'u' and 'z' to be determined at datum plane 'h' 2. datum 'd' and 'e' to be determined at seating plane datum 'y'. 3. dimension 'd1' and 'e1' do not include mold protrusions. allowable protrusion is 0.25 per side. dimensions 'd1' and 'e1' do include mold mismatch and are determined at datum plane datum 'h'. 4. dimension 'b' does not include dambar protrusion. allowable dambar protrusion shall not cause thelead width to exceed the maxi- mum 'b' dimension by more than 0.08 mm. dambar can not be locatedon the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. 5. exact shape of each corner is optional. table 7.1. lqfp100 (dimensions in mm) symbol min nom max total thickness a 1.6 stand off a1 0.05 0.15 mold thickness a2 1.35 1.4 1.45 lead width (plating) b 0.17 0.2 0.27 lead width b1 0.17 0.23 l/f thickness (plating) c 0.09 0.2 lead thickness c1 0.09 0.16 EFM32G data sheet lqfp100 package specifications silabs.com | building a more connected world. rev. 2.10 | 170 symbol min nom max x d 16 bsc y e 16 bsc body size x d1 14 bsc y e1 14 bsc lead pitch e 0.5 bsc l 0.45 0.6 0.75 footprint l1 1 ref 0o 3.5o 7o 1 0o 2 11o 12o 13o 3 11o 12o 13o r1 0.08 r1 0.08 0.2 s 0.2 package edge tolerance aaa 0.2 lead edge tolerance bbb 0.2 coplanarity ccc 0.08 lead offset ddd 0.08 mold flatness eee 0.05 the lqfp100 package uses nickel-palladium-gold preplated leadframe. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx EFM32G data sheet lqfp100 package specifications silabs.com | building a more connected world. rev. 2.10 | 171 7.2 lqfp100 pcb layout e a d c b p1 p2 p3 p4 p5 p6 p7p8 figure 7.2. lqfp100 pcb land pattern table 7.2. lqfp100 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) symbol pin number symbol pin number a 1.45 p1 1 p6 75 b 0.30 p2 25 p7 76 c 0.50 p3 26 p8 100 d 15.40 p4 50 e 15.40 p5 51 e a d c b figure 7.3. lqfp100 pcb solder mask table 7.3. lqfp100 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) a 1.57 b 0.42 c 0.50 d 15.40 e 15.40 EFM32G data sheet lqfp100 package specifications silabs.com | building a more connected world. rev. 2.10 | 172 e a d c b figure 7.4. lqfp100 pcb stencil design table 7.4. lqfp100 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) a 1.35 b 0.20 c 0.50 d 15.40 e 15.40 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see pin definitions. EFM32G data sheet lqfp100 package specifications silabs.com | building a more connected world. rev. 2.10 | 173 7.3 lqfp100 package marking in the illustration below package fields and position are shown. figure 7.5. example chip marking (top view) EFM32G data sheet lqfp100 package specifications silabs.com | building a more connected world. rev. 2.10 | 174 8. tqfp64 package specifications 8.1 tqfp64 package dimensions rev: 98spp64023a_xo1_17mar2011 c l f figure 8.1. tqfp64 note: 1. all dimensions & tolerancing confirm to asme y14.5m-1994. 2. the top package body size may be smaller than the bottom package body size. 3. datum 'a,b', and 'b' to be determined at datum plane 'h'. 4. to be determined at seating place 'c'. 5. dimension 'd1' and 'e1' do not include mold protrusions. allowable protrusion is 0.25mm per side.'d1' and 'e1' are maximum plas- tic body size dimension including mold mismatch. dimension 'd1' and'e1' shall be determined at datum plane 'h'. 6. detail of pin 1 indicatifier are option all but must be located within the zone indicated. 7. dimension 'b' does not include dambar protrusion. allowable dambar protrusion shall not cause thelead width to exceed the maxi- mum 'b' dimension by more than 0.08 mm. dambar can not be locatedon the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07 mm. 8. exact shape of each corner is optional. 9. these dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 10. all dimensions are in millimeters. table 8.1. qfp64 (dimensions in mm) dim min nom max dim min nom max a 1.10 1.20 l1 a1 0.05 0.15 r1 0.08 a2 0.95 1.00 1.05 r2 0.08 0.20 EFM32G data sheet tqfp64 package specifications silabs.com | building a more connected world. rev. 2.10 | 175 dim min nom max dim min nom max b 0.17 0.22 0.27 s 0.20 b1 0.17 0.20 0.23 0 3.5 7 c 0.09 0.20 1 0 c1 0.09 0.16 2 11 12 13 d 12.0 bsc 3 11 12 13 d1 10.0 bsc e 0.50 bsc e 12.0 bsc e1 10.0 bsc l 0.45 0.60 0.75 the tqfp64 package is 10 by 10 mm in size and has a 0.5 mm pin pitch. the tqfp64 package uses nickel-palladium-gold preplated leadframe. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx . EFM32G data sheet tqfp64 package specifications silabs.com | building a more connected world. rev. 2.10 | 176 8.2 tqfp64 pcb layout e a d c b p1 p2 p3 p4 p5 p6 p7p8 figure 8.2. tqfp64 pcb land pattern table 8.2. tqfp64 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) symbol pin number symbol pin number a 1.60 p1 1 p6 48 b 0.30 p2 16 p7 49 c 0.50 p3 17 p8 64 d 11.50 p4 32 e 11.50 p5 33 e a d c b figure 8.3. tqfp64 pcb solder mask table 8.3. tqfp64 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) a 1.72 b 0.42 c 0.50 d 11.50 e 11.50 EFM32G data sheet tqfp64 package specifications silabs.com | building a more connected world. rev. 2.10 | 177 e a d c b figure 8.4. tqfp64 pcb stencil design table 8.4. tqfp64 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) a 1.50 b 0.20 c 0.50 d 11.50 e 11.50 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see pin definitions. EFM32G data sheet tqfp64 package specifications silabs.com | building a more connected world. rev. 2.10 | 178 8.3 tqfp64 package marking in the illustration below package fields and position are shown. figure 8.5. example chip marking (top view) EFM32G data sheet tqfp64 package specifications silabs.com | building a more connected world. rev. 2.10 | 179 9. tqfp48 package specifications 9.1 tqfp48 package dimensions rev: 98spp48097a_xo_30mar11 figure 9.1. tqfp48 note: 1. dimensions and tolerance per asme y14.5m-1994 2. control dimension: millimeter 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead existsfrom the plastic body at the bot- tom of the parting line. 4. datums t, u and z to be determined at datum plane ab. 5. dimensions s and v to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimensionto exceed 0.350. 8. minimum solder plate thickness shall be 0.0076. 9. exact shape of each corner is optional. table 9.1. qfp48 (dimensions in mm) dim min nom max dim min nom max a 7.000 bsc m 12deg ref a1 3.500 bsc n 0.090 0.160 b 7.000 bsc p 0.250 bsc b1 3.500 bsc r 0.150 0.250 c 1.000 1.200 s 9.000 bsc EFM32G data sheet tqfp48 package specifications silabs.com | building a more connected world. rev. 2.10 | 180 dim min nom max dim min nom max d 0.170 0.270 s1 4.500 bsc e 0.950 1.050 v 9.000 bsc f 0.170 0.230 v1 4.5000 bsc g 0.500 bsc w 0.200 bsc h 0.050 0.150 aa 1.000bsc j 0.090 0.200 k 0.500 0.700 l 0de g 7deg the tqfp48 package is 7 by 7 mm in size and has a 0.5 mm pin pitch. the tqfp48 package uses nickel-palladium-gold preplated leadframe. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx EFM32G data sheet tqfp48 package specifications silabs.com | building a more connected world. rev. 2.10 | 181 9.2 tqfp48 pcb layout e a d c b p1 p2 p3 p4 p5 p6 p7p8 figure 9.2. tqfp48 pcb land pattern table 9.2. tqfp48 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) symbol pin number symbol pin number a 1.60 p1 1 p6 36 b 0.30 p2 12 p7 37 c 0.50 p3 13 p8 48 d 8.50 p4 24 e 8.50 p5 25 e a d c b figure 9.3. tqfp48 pcb solder mask table 9.3. tqfp48 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) a 1.72 b 0.42 c 0.50 d 8.50 e 8.50 EFM32G data sheet tqfp48 package specifications silabs.com | building a more connected world. rev. 2.10 | 182 e a d c b figure 9.4. tqfp48 pcb stencil design table 9.4. tqfp48 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) a 1.50 b 0.20 c 0.50 d 8.50 e 8.50 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see 5. pin definitions . EFM32G data sheet tqfp48 package specifications silabs.com | building a more connected world. rev. 2.10 | 183 9.3 tqfp48 package marking in the illustration below package fields and position are shown. figure 9.5. example chip marking (top view) EFM32G data sheet tqfp48 package specifications silabs.com | building a more connected world. rev. 2.10 | 184 10. qfn64 package specifications 10.1 qfn64 package dimensions rev: 98spp64048a_xo1_08mar2011 16 17 32 33 64 1 49 48 m m figure 10.1. qfn64 note: 1. dimensioning & tolerancing confirm to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. dimension l1 represents terminal full back from package edge up to 0.1 mm isacceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. table 10.1. qfn64 (dimensions in mm) symbol min nom max a 0.80 0.85 0.90 a1 0.00 0.05 a3 0.203 ref b 0.25 0.30 0.35 d 9.00 bsc e 9.00 bsc d2 7.10 7.20 7.30 e2 7.10 7.20 7.30 EFM32G data sheet qfn64 package specifications silabs.com | building a more connected world. rev. 2.10 | 185 symbol min nom max e 0.50 bsc l 0.40 0.45 0.50 l1 0.00 0.10 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 the qfn64 package uses nickel-palladium-gold preplated leadframe. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx . EFM32G data sheet qfn64 package specifications silabs.com | building a more connected world. rev. 2.10 | 186 10.2 qfn64 pcb layout e a d p1 p2 p3 p4 p5 p6 p7 p8 c b p9 f g figure 10.2. qfn64 pcb land pattern table 10.2. qfn64 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) symbol pin number symbol pin number a 0.85 p1 1 p8 64 b 0.30 p2 16 p9 65 c 0.50 p3 17 d 8.90 p4 32 e 8.90 p5 33 f 7.20 p6 48 g 7.20 p7 49 e a d c b f g figure 10.3. qfn64 pcb solder mask table 10.3. qfn64 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) symbol dim. (mm) a 0.97 e 8.90 b 0.42 f 7.32 c 0.50 g 7.32 EFM32G data sheet qfn64 package specifications silabs.com | building a more connected world. rev. 2.10 | 187 symbol dim. (mm) symbol dim. (mm) d 8.90 - - e a d c b x y z figure 10.4. qfn64 pcb stencil design table 10.4. qfn64 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) symbol dim. (mm) a 0.75 e 8.90 b 0.22 x 2.70 c 0.50 y 2.70 d 8.90 z 0.80 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see pin definitions. EFM32G data sheet qfn64 package specifications silabs.com | building a more connected world. rev. 2.10 | 188 10.3 qfn64 package marking in the illustration below package fields and position are shown. figure 10.5. example chip marking (top view) EFM32G data sheet qfn64 package specifications silabs.com | building a more connected world. rev. 2.10 | 189 11. qfn32 package specifications 11.1 qfn32 package dimensions rev: 98spp32088a_xo1_10mar2011 d e d2 32xl e2 e 32xb m m m g m 1 17 32 9 2 3 4 5 6 7 8 31 30 29 28 27 26 25 18 19 20 21 22 23 24 10 11 12 13 14 15 16 even / odd terminl side e l1 l detail g view rotated 90 clockwise a3 a a1 seating plane figure 11.1. qfn32 note: 1. dimensioning & tolerancing confirm to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. dimension l1 represents terminal full back from package edge up to 0.1 mm isacceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. table 11.1. qfn32 (dimensions in mm) symbol a a1 a3 b d e d2 e2 e l l1 aaa bbb ccc ddd eee min 0.80 0.00 0.203 ref 0.25 6.00 bsc 6.00 bsc 4.30 4.30 0.65 bsc 0.30 0.00 0.10 0.10 0.10 0.05 0.08 nom 0.85 0.30 4.40 4.40 0.35 max 0.90 0.05 0.35 4.50 4.50 0.40 0.10 the qfn32 package uses nickel-palladium-gold preplated leadframe. all efm32 packages are rohs compliant and free of bromine (br) and antimony (sb). for additional quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx EFM32G data sheet qfn32 package specifications silabs.com | building a more connected world. rev. 2.10 | 190 11.2 qfn32 pcb layout e a d p1 p2 p3 p4 p5 p6 p7 p8 c b p9 f g figure 11.2. qfn32 pcb land pattern table 11.2. qfn32 pcb land pattern dimensions (dimensions in mm) symbol dim. (mm) symbol pin number symbol pin number a 0.80 p1 1 p6 24 b 0.35 p2 8 p7 25 c 0.65 p3 9 p8 32 d 6.00 p4 16 p9 33 e 6.00 p5 17 f 4.40 g 4.40 e a d c b f g figure 11.3. qfn32 pcb solder mask table 11.3. qfn32 pcb solder mask dimensions (dimensions in mm) symbol dim. (mm) a 0.92 b 0.47 c 0.65 EFM32G data sheet qfn32 package specifications silabs.com | building a more connected world. rev. 2.10 | 191 symbol dim. (mm) d 6.00 e 6.00 f 4.52 g 4.52 e a d c b x y z figure 11.4. qfn32 pcb stencil design table 11.4. qfn32 pcb stencil design dimensions (dimensions in mm) symbol dim. (mm) a 0.70 b 0.25 c 0.65 d 6.00 e 6.00 x 1.30 y 1.30 z 0.50 note: 1. the drawings are not to scale. 2. all dimensions are in millimeters. 3. all drawings are subject to change without notice. 4. the pcb land pattern drawing is in compliance with ipc-7351b. 5. stencil thickness 0.125 mm. 6. for detailed pin-positioning, see 5. pin definitions . EFM32G data sheet qfn32 package specifications silabs.com | building a more connected world. rev. 2.10 | 192 11.3 qfn32 package marking in the illustration below package fields and position are shown. figure 11.5. example chip marking (top view) EFM32G data sheet qfn32 package specifications silabs.com | building a more connected world. rev. 2.10 | 193 12. chip revision, solder information, errata 12.1 chip revision the revision of a chip can be determined from the "revision" field in the package marking. 12.2 soldering information the latest ipc/jedec j-std-020 recommendations for pb-free reflow soldering should be followed. 12.3 errata please see the errata document for description and resolution of device errata. this document is available in simplicity studio and on- line at: http://www.silabs.com/support/pages/document-library.aspx?p=mcus--32-bit EFM32G data sheet chip revision, solder information, errata silabs.com | building a more connected world. rev. 2.10 | 194 13. revision history 13.1 revision 2.10 july 19, 2017 in 4.8 general purpose input output : ? added missing multiply symbols. in 4.10 analog digital converter (adc) : ? updated average active current. ? updated snr. ? updated sinad. ? updated sfdr. ? renamed vref output voltage to vref voltage. in 4.11 digital analog converter (dac) : ? renamed vref output voltage to vref voltage. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 195 13.2 revision 2.00 may 10th, 2017 consolidated all EFM32G data sheets: ? EFM32G200 ? EFM32G210 ? EFM32G222 ? EFM32G230 ? EFM32G232 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G842 ? EFM32G880 ? EFM32G890 new formatting throughout. added 1. feature list . updated ordering codes in 2. ordering information for revision e and tape and reel. added figure 2.1 ordering code decoder on page 5 . separated memory map figure into figure 3.2 system address space with core and code space listing on page 27 and figure 3.3 system address space with peripheral listing on page 28 for readability. removed footnote for storage temperature range in 4.2 absolute maximum ratings . in 4.6 power management : ? updated em0 condition for v bodextthr- specification. ? added v bodextthr- in em1 and em2 specifications. ? updated em0 condition for v bodextthr+ specification. updated flash page erase time and device erase time in 4.7 flash and added footnotes. updated figures in 4.9.3 lfrco . updated figures and hfrco current consumption typical values in 4.9.4 hfrco . in 4.10 analog digital converter (adc) : ? updated test conditions, updated specifications, and added footnote for average active current. ? added input bias current. ? added input offset current. ? updated adc clock frequency. ? updated snr, sinad and sfdr. ? updated offset voltage. ? updated missing codes. ? added gain error drift and offset error drift. ? added vref output voltage, vref voltage drift, vref temperature drift, vref current consumption, and adc and dac vref matching. in 4.11 digital analog converter (dac) : ? updated i dac parameter, test conditions, and footnote. ? added dac load current specification to 4.11 digital analog converter (dac) . ? added vref output voltage, vref voltage drift, vref temperature drift, vref current consumption, and adc and dac vref matching. updated acmp active current (biasprog=0b1111, fullbias=1 and halfbias=0 in acmpn_ctrl register) typical value in 4.12 analog comparator (acmp) . updated vcmp hysteresis typical value in 4.13 voltage comparator (vcmp) . EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 196 corrected pin number for symbol p3 in table 11.2 qfn32 pcb land pattern dimensions (dimensions in mm) on page 191 . updated package marking figures to include temperature grade. 13.3 revision 1.90 may 22nd, 2015 for devices with an adc, added clarification on conditions for inl adc and dnl adc parameters. corrected em2 current consumption condition in electrical characteristics section. added auxhfrco to block diagram and electrical characteristics. updated hfrco table in the electrical characteristics section. updated em0, em2, em3, and em4 maximum current specifications in the electrical characteristics section. updated the output low voltage maximum for sinking 20 ma with vdd = 3.0 v in the electrical characteristics section. updated the input leakage current maximum in the electrical characteristics section. updated the minimum and maximum frequency specifications for the lfrco, hfrco, and auxhfrco in the electrical characteris- tics section. updated the maximum current consumption of the hfrco in the electrical characteristics section. updated the maximum current consumption of the hfrco in the electrical characteristics section. added some minimum adc snr, sndr, and sfdr specifications in the electrical characteristics section. added some minimum and maximum adc offset voltage, dnl, and inl specifications in the electrical characteristics section. added maximum dac current specifications in the electrical characteristics section. added maximum acmp current and maximum and minimum offset voltage specifications in the electrical characteristics section. added maximum vcmp current and updated typical vcmp current specifications in the electrical characteristics section. updated references to energyaware designer to configurator. 13.4 revision 1.80 july 2nd, 2014 corrected single power supply voltage minimum value from 1.85v to 1.98v. updated current consumption. updated transition between energy modes. updated power management data. updated gpio data. updated lfxo, hfxo, hfrco and ulfrco data. updated lfrco and hfrco plots. for devices with an acmp, updated acmp data. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 197 13.5 revision 1.71 november 21st, 2013 updated figures. updated errata-link. updated chip marking. added link to environmental and quality information. for devices with a dac, re-added missing dac-data. 13.6 revision 1.70 september 30th, 2013 for devices with an i2c, added i2c characterization data. corrected gpio operating voltage from 1.8 v to 1.85 v. for devices with an adc, corrected the adc resolution from 12, 10 and 6 bit to 12, 8 and 6 bit. for qfn64 devices, updated the max v esdcdm value to 750 v. updated environmental information. updated trademark, disclaimer and contact information. other minor corrections. 13.7 revision 1.60 june 28th, 2013 for bga devices, updated pcb land pattern, pcb solder mask and pcb stencil design figures. updated power requirements in the power management section. removed minimum load capacitance figure and table. added reference to application note. other minor corrections. 13.8 revision 1.50 september 11th, 2012 updated the hfrco 1 mhz band typical value to 1.2 mhz. updated the hfrco 7 mhz band typical value to 6.6 mhz. for bga devices, corrected bga solder balls material from sn96.5/ag3/cu0.5 to sac105. other minor corrections. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 198 13.9 revision 1.40 february 27th, 2012 updated power management section. corrected operating voltage from 1.8 v to 1.85 v. corrected tgrad adcth parameter. corrected package drawing. updated pcb land pattern, solder mask and stencil design. for lqfp48 devices, corrected available pulse counters from 3 to 2. for lqfp48 devices, corrected available leuarts from 2 to 1. for lqfp64 devices, corrected ordering codes in the ordering information table. 13.10 revision 1.30 may 20th, 2011 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 updated lfxo load capacitance section. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 199 13.11 revision 1.20 december 17th, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 increased max storage temperature. added data for <150c and <70c on flash data retention. changed latch-up sensitivity test description. added io leakage current. for lqfp100 devices, updated esd cdm value. added flash current consumption. updated hfrco data. updated lfrco data. added graph for adc absolute offset over temperature. added graph for adc temperature sensor readout. 13.12 revision 1.11 november 17th, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 corrected maximum dac clock speed for continuous mode. added dac sample-hold mode voltage drift rate. added pulse widths detected by the hfxo glitch detector. added power sequencing information to power management section. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 200 13.13 revision 1.10 september 13th, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 for lqfp100 devices, corrected number of gpio pins. added typical values for r adcfilt and c adcfilt . added two conditions for dac clock frequency; one for sample/hold and one for sample/off. added rohs information and specified leadframe/solderballs material. added serial bootloader to feature list and system summary. updated adc characterization data. updated dac characterization data. updated rco characterization data. updated acmp characterization data. updated vcmp characterization data. 13.14 revision 1.00 april 23rd, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 adc_vcm line removed. added pinout illustration and additional pinout table. changed "errata" chapter. errata description moved to separate document. document changed status from "preliminary". updated "electrical characteristics" chapter. for EFM32G222 may 20th, 2011 updated lfxo load capacitance section. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 201 13.15 revision 0.90 this revision applies the following devices: ? EFM32G222 initial preliminary revision, april 14th, 2011 this revision applies the following devices: ? EFM32G232 ? EFM32G842 initial preliminary revision, june 30th, 2011 13.16 revision 0.85 february 19th, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 renamed dbg_swv pin to dbg_swo. 13.17 revision 0.84 february 11th, 2010 this revision applies the following devices: ? EFM32G230 ? EFM32G840 corrected pinout tables. 13.18 revision 0.83 january 25th, 2010 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 updated errata section. specified flash word width in flash electrical characteristics. added capacitive sense internal resistor values in acmp electrical characteristics. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 202 13.19 revision 0.82 december 9th, 2009 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 for lqfp100 devices, incorrect pin 0 removed from pinout table. updated contact information. adc current consumption numbers updated in adc electrical characteristics. for devices with lcd, updated lcd supply voltage range in lcd electrical characteristics. 13.20 revision 0.81 november 20th, 2009 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 for devices without a differential dac, system summary updated. electrical characteristics updated. storage temperature in electrical characteristics updated. temperature coefficient of band-gap reference in electrical characteristics added. erase times in flash electrical characteristics updated. definitions of dnl and inl added in adc section. for devices with and lcd, lcd electrical characteristics added. current consumption of digital peripherals added in electrical characteristics. for lqfp100 devices, package information in pinout and package corrected. for bga112 devices, pinout information in pinout table corrected. updated errata section. EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 203 13.21 revision 0.80 october 19th, 2009 this revision applies the following devices: ? EFM32G200 ? EFM32G210 ? EFM32G230 ? EFM32G280 ? EFM32G290 ? EFM32G840 ? EFM32G880 ? EFM32G890 initial preliminary revision EFM32G data sheet revision history silabs.com | building a more connected world. rev. 2.10 | 204 http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa simplicity studio one-click access to mcu and wireless tools, documentation, software, source code libraries & more. available for windows, mac and linux! iot portfolio www.silabs.com/iot sw/hw www.silabs.com/simplicity quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon labs products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon labs shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon labs. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon labs products are not designed or authorized for military applications. silicon labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, micrium, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? , zentri and others are trademarks or registered trademarks of silicon labs. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. |
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